LSM330DL datasheet(42/54 Pages) STMICROELECTRONICS

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Registers description

LSM330DL

42/54

Doc ID 022018 Rev 1

7.28

CTRL_REG5_G (24h)

Figure 12.

INT1_Sel and Out_Sel configuration block diagram

FS1-FS0

Full-scale selection. Default value: 00

(00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)

SIM

SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 74.

CTRL_REG4_G description (continued)

Table 75.

CTRL_REG5_G register

BOOT

FIFO_EN

HPen

INT1_Sel1

INT1_Sel0

Out_Sel1

Out_Sel0

Table 76.

CTRL_REG5_G description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO_EN

FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO Enable)

HPen

High-pass filter enable. Default value: 0

(0: HPF disabled; 1: HPF enabled See

Figure 12: INT1_Sel and Out_Sel config-

uration block diagram)

INT1_Sel1-

INT1_Sel0

INT1 selection configuration. Default value: 0

(See

Figure 12: INT1_Sel and Out_Sel configuration block diagram)

Out_Sel1-

Out_Sel1

Out selection configuration. Default value: 0

(See

Figure 12: INT1_Sel and Out_Sel configuration block diagram)

ADC

LPF1

HPF

HPen

LPF2

Out_Sel <1:0>

DataReg

FIFO

32x16x3

Interrupt

generator

INT1_Sel <1:0>

AM09276V1

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