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ANSELA 数据表(PDF) 30 Page - Microchip Technology |
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ANSELA 数据表(HTML) 30 Page - Microchip Technology |
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30 / 222 page  MCP19111 DS22331A-page 30 2013 Microchip Technology Inc. FIGURE 5-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TABLE 5-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER REQUIREMENTS Param No. Sym Characteristic Min Typ† Max Units Conditions 30 TMCL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40°C to +85°C 31 TWDT Watchdog Timer Time-out Period (No Prescaler) 718 33 ms VDD = 5V, -40°C to +85°C 32 TOST Oscillation Start-up Timer Period — 1024TOSC —— TOSC = OSC1 period 33* TPWRT Power up Timer Period (4 x TWDT) 28 64 132 ms VDD = 5V, -40°C to +85°C 34 TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset —— 2.0 µs * These parameters are characterized but not tested. † Data in “Typ” column is at VIN =12V (VDD = 5V), +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 5-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic Min Typ† Max Units Conditions 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns With Prescaler 10 — — ns 42* Tt0P T0CKI Period Greater of: 20 or TCY + 40 N — — ns N = prescale value (2, 4, ..., 256) * These parameters are characterized but not tested. † Data in “Typ” column is at VIN =12V (VDD = 5V), +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 41 42 40 T0CKI |
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