ANSELA datasheet(92/222 Pages) MICROCHIP

92 / 222 page

MCP19111

DS22331A-page 92

 2013 Microchip Technology Inc.

FIGURE 15-1:

INTERRUPT LOGIC

FIGURE 15-2:

INT PIN INTERRUPT TIMING

TMR1IF

TMR1IE

SSPIF

SSPIE

T0IF

T0IE

INTF

INTE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

PEIF

ADIF

ADIE

UVIF

UVIE

OVIF

OVIE

OCIF

OCIE

VINIF

VINIE

BCLIF

BCLIE

TMR2IF

TMR2IE

IOCF

IOCE

Q3 Q4

CLKIN

CLKOUT

INT pin

INTF flag

(INTCON reg.)

GIE bit

(INTCON reg.)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 5.0 “Digital Electrical Characteristics”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

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