ANSELA datasheet(76/222 Pages) MICROCHIP

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MCP19111

DS22331A-page 76

 2013 Microchip Technology Inc.

11.4

PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 11-2 shows the two

situations for loading the PC. The upper example in

Figure 11-2 shows how the PC is loaded on a write to PCL

(PCLATH<4:0>

 PCH).

The

lower

example

Figure 11-2 shows how the PC is loaded during a CALL or

GOTO

instruction (PCLATH<4:3>

 PCH).

FIGURE 11-2:

LOADING OF PC IN

DIFFERENT SITUATIONS

11.4.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination

simultaneously

causes

the

Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

content of the program counter to be changed by

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are written to the PCL register, all

13 bits of the program counter will change to the values

contained in the PCLATH register and those being

written to the PCL register.

11.4.2

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFFh to 0X00h in the middle

of the table, then PCLATH must be incremented for

each address rollover that occurs between the table

beginning and the table location within the table.

For more information, refer to Application Note AN556

– “Implementing a Table Read” (DS00556).

11.4.3

COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

11.4.4

STACK

The MCP19111 has an 8-level x 1-bit wide hardware

stack (refer to Figure 11-1). The stack space is not part

of either program or data space and the Stack Pointer

is not readable or writable. The PC is PUSHed onto the

stack when CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN

, RETLW or a RETFIE instruction execution.

PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

11.5

Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register directly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR and the IRP bit of the

STATUS register, as shown in Figure 11-3.

A simple program to clear RAM location 40h-7Fh using

indirect addressing is shown in Example 11-3.

8 7

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO

, CALL

Opcode <10:0>

12 11 10

PCLATH<4:3>

PCH

PCL

PCLATH

PCH

PCL

Destination

Note 1: There are no Status bits to indicate Stack

Overflow or Stack Underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL

RETURN

RETLW

and RETFIE

instructions

the

vectoring

interrupt address.

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