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DS22331A-page 91

MCP19111

15.0

INTERRUPTS

The MCP19111 has multiple sources of interrupt:

• External Interrupt (INT pin)

• Interrupt-On-Change (IOC) Interrupts

• Timer0 Overflow Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• ADC Interrupt

• System Overvoltage Error

• System Under Voltage Error

• System Overcurrent Error

• SSP

•BCL

• System Input Under Voltage Error

The Interrupt Control register (INTCON) and Peripheral

Interrupt Request Registers (PIRx) record individual

interrupt requests in flag bits. The INTCON register

also has individual and global interrupt enable bits.

The Global Interrupt Enable bit, GIE of the INTCON

disables (if cleared) all interrupts. Individual interrupts

can be disabled through their corresponding enable

bits in the INTCON register and PIEx registers. GIE is

cleared on Reset.

When an interrupt is serviced, the following actions

occur automatically:

• The GIE is cleared to disable any further interrupt.

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR, to avoid repeated

interrupts. Because the GEI bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exists the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific interrupt’s oper-

ation, refer to its peripheral chapter.

15.1

Interrupt Latency

For external interrupt events, such as the INT pin or

PORTGPx change interrupt, the interrupt latency will

be three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 15-2). The latency is the same for one or

two-cycle instructions.

15.2

GPA2/INT Interrupt

The external interrupt on the GPA2/INT pin is

edge-triggered; either on the rising edge, if the INTEDG

bit of the OPTION register is set, or the falling edge, if

the INTEDG bit is cleared. When a valid edge appears

on the GPA2/INT pin, the INTF bit of the INTCON

clearing the INTE control bit of the INTCON register.

The INTF bit must be cleared by software in the

Interrupt Service Routine before re-enabling this

interrupt. The GPA2/INT interrupt can wake-up the

processor from Sleep, if the INTE bit was set prior to

going into Sleep. See Section 16.0 “Power-Down

Mode (Sleep)” for details on Sleep, and Section 16.1

“Wake-up from Sleep” for timing of wake-up from

Sleep through GPA2/INT interrupt.

Note 1: Individual interrupt flag bits are set,

regardless

the

status

their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

Note:

The ANSEL register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs

will read ‘0’ and cannot generate an

interrupt.

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