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ANSELA 数据表(PDF) 134 Page - Microchip Technology |
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ANSELA 数据表(HTML) 134 Page - Microchip Technology |
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134 / 222 page  MCP19111 DS22331A-page 134 2013 Microchip Technology Inc. 23.1.4 SWITCHING PRESCALER BETWEEN TIMER0 AND WDT MODULES As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 23-1 must be executed. EXAMPLE 23-1: CHANGING PRESCALER (TIMER0 WDT) When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 23-2). EXAMPLE 23-2: CHANGING PRESCALER (WDT TIMER0) 23.1.5 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit can only be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. 23.1.6 USING TIMER0 WITH AN EXTERNAL CLOCK When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 5.0 “Digital Electrical Characteristics”. 23.1.7 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. BANKSEL TMR0 ; CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and ;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ; ; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32 CLRWDT ;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b’00000011’ ;Set prescale to 1:16 MOVWF OPTION_REG ; Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 94 OPTION_REG RAUP INTEDG T0CS T0SE PSA PS2 PS1 PS0 75 TMR0 Timer0 Module Register 133* TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 112 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. |
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