STM32F303VC datasheet(93/133 Pages) STMICROELECTRONICS

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STM32F302xx/STM32F303xx

Electrical characteristics

Doc ID 023353 Rev 5

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Figure 24.

Recommended NRST pin protection

The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 55. Otherwise the reset will not be taken into account by the device.

6.3.16

Timer characteristics

The parameters given in Table 56 are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(NPOR)

(1)

Guaranteed by design, not tested in production.

NPOR Input low level voltage

0.475VDDA

- 0.2

VIH(NPOR)

(1)

NPOR Input high level voltage

0.5VDDA

+ 0.2

Vhys(NPOR)

(1) NPOR Schmitt trigger voltage

hysteresis

200

RPU

Weak pull-up equivalent resistor(2)

The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance is minimal (~10% order).

VIN = VSS

Table 56.

TIMx(1) characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

tres(TIM)

(2)

Timer resolution time

tTIMxCLK

fTIMxCLK = 72 MHz

(except TIM1/8)

13.9

fTIMxCLK = 144 MHz,

x= 1.8

6.95

fEXT

(2)

Timer external clock

frequency on CH1 to CH4

fTIMxCLK/2

MHz

fTIMxCLK = 72 MHz

MHz

ResTIM

(2)

Timer resolution

TIMx (except TIM2)

bit

TIM2

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