STM32F303VC datasheet(98/133 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F302xx/STM32F303xx

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Doc ID 023353 Rev 5

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Table 61 for SPI or in Table 62 for I2S

are derived from tests performed under ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized in Table 22.

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Table 61.

SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

(1)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

(1)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

DuCy(SCK)(1)

SPI slave input clock

duty cycle

Slave mode

tsu(NSS)

(1)

Data based on characterization results, not tested in production.

NSS setup time

Slave mode

2Tpclk

th(NSS)

(1)

NSS hold time

Slave mode

4Tpclk

tw(SCKH)

(1)

tw(SCKL)

(1)

SCK high and low time

Master mode, fPCLK = 36 MHz,

presc = 4

Tpclk/2

- 3

Tpclk/2

+ 3

tsu(MI)

(1)

tsu(SI)

(1)

Data input setup time

Master mode

5.5

Slave mode

6.5

th(MI)

(1)

Data input hold time

Master mode

th(SI)

(1)

Slave mode

ta(SO)

(1)(2)

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

Data output access time Slave mode, fPCLK = 24 MHz

4Tpclk

tdis(SO)

(1)(3)

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z.

Data output disable time Slave mode

tv(SO)

(1)

Data output valid time

Slave mode (after enable edge)

tv(MO)

(1)

Data output valid time

Master mode (after enable edge)

th(SO)

(1)

Data output hold time

Slave mode (after enable edge)

th(MO)

(1)

Master mode (after enable edge)

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