STM32F303VC datasheet(26/133 Pages) STMICROELECTRONICS

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Functional overview

STM32F302xx/STM32F303xx

26/133

Doc ID 023353 Rev 5

3.18

Inter-integrated circuit interface (I2C)

Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support

standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.

Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses

(2 addresses, 1 with configurable mask). They also include programmable analog and

digital noise filters.

In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. They also have a clock domain independent from the CPU

clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller.

Refer to Table 5 for the features available in I2C1 and I2C2.

Table 4.

Comparison of I2C analog and digital filters

Analog filter

Digital filter

Pulse width of

suppressed spikes

≥ 50 ns

Programmable length from 1 to 15

I2C peripheral clocks

Benefits

Available in Stop mode

1. Extra filtering capability vs.

standard requirements.

2. Stable length

Drawbacks

Variations depending on

temperature, voltage, process

Disabled when Wakeup from Stop

mode is enabled

Table 5.

STM32F30xB/C I2C implementation

I2C features(1)

X = supported.

I2C1

I2C2

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

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