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STM32F303VC 数据表(PDF) 100 Page - STMicroelectronics |
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STM32F303VC 数据表(HTML) 100 Page - STMicroelectronics |
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100 / 133 page  Electrical characteristics STM32F302xx/STM32F303xx 100/133 Doc ID 023353 Rev 5 Figure 28. SPI timing diagram - master mode(1) 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Table 62. I2S characteristics Symbol Parameter Conditions Min Max Unit fCK 1/tc(CK) (1) I2S clock frequency Master data: 16 bits, audio freq=48 kHz 1.496 1.503 MHz Slave 0 12.288 tr(CK) tf(CK) (1) I2S clock rise and fall time Capacitive load CL =30pF -8 ns tw(CKH) (1) I2S clock high time Master fPCLK= 36 MHz, audio frequency = 48 kHz 331 - tw(CKL) (1) I2S clock low time 332 - tv(WS) (1) WS valid time Master mode 4 - th(WS) (1) WS hold time Master mode 4 - tsu(WS) (1) WS setup time Slave mode 4 - th(WS) (1) WS hold time Slave mode 0 - Duty Cycle(1) I2S slave input clock duty cycle Slave mode 30 70 % |
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