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STM32F303VC 数据表(PDF) 101 Page - STMicroelectronics |
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STM32F303VC 数据表(HTML) 101 Page - STMicroelectronics |
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101 / 133 page ![]() STM32F302xx/STM32F303xx Electrical characteristics Doc ID 023353 Rev 5 101/133 Figure 29. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at 0.5VDD and with external CL=30 pF 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. tsu(SD_MR) (1) Data input setup time Master receiver 9 ns tsu(SD_SR) (1) Data input setup time Slave receiver 2 th(SD_MR) (1) Data input hold time Master receiver 0 th(SD_SR) (1) Slave receiver 0 tv(SD_ST) (1) Data output valid time Slave transmitter (after enable edge) 29 th(SD_ST) (1) Data output hold time Slave transmitter (after enable edge) 12 tv(SD_MT) (1) Data output valid time Master transmitter (after enable edge) 3 th(SD_MT) (1) Data output hold time Master transmitter (after enable edge) 2 1. Data based on characterization results, not tested in production. Table 62. I2S characteristics (continued) Symbol Parameter Conditions Min Max Unit CPOL = 0 CPOL = 1 tc(CK) WS input SDtransmit SDreceive tw(CKH) tw(CKL) tsu(WS) tv(SD_ST) th(SD_ST) th(WS) tsu(SD_SR) th(SD_SR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14881b LSB receive(2) LSB transmit(2) |
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