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LSM9DS0 数据表(PDF) 62 Page - STMicroelectronics |
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LSM9DS0 数据表(HTML) 62 Page - STMicroelectronics |
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62 / 74 page ![]() Register description LSM9DS0 62/74 DocID024763 Rev 2 8.48 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) Y-axis acceleration data. The value is expressed in 16-bit as two’s complement left justified. 8.49 OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) Z-axis acceleration data. The value is expressed in 16-bit as two’s complement left justified. 8.50 FIFO_CTRL_REG (2Eh) Interrupt generator 2 can change the FIFO mode. 8.51 FIFO_SRC_REG (2Fh) Table 94. FIFO_CTRL_REG register FM2 FM1 FM0 FTH4 FTH3 FTH2 FTH1 FTH0 Table 95. FIFO_CTRL_REG description FM2-FM0 FIFO mode selection. Default value: 000 FTH4-FTH0 FIFO watermark level. Default value: 00000 Table 96. FIFO mode configuration FM2 FM1 FM0 FIFO mode 0 0 0 Bypass mode 0 0 1 FIFO mode 0 1 0 Stream mode 0 1 1 Stream-to-FIFO mode 1 0 0 Bypass-to-Stream mode Table 97. FIFO_SRC_REG register WTM OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 Table 98. FIFO_SRC_REG description WTM Watermark status. WTM bit is set to ‘1’ when FIFO content exceeds watermark level. OVRN FIFO Overrun status. OVRN bit is set to ‘1’ when FIFO buffer is full. |
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