LSM9DS0 datasheet(44/74 Pages) STMICROELECTRONICS

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LSM9DS0

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DocID024763 Rev 2

8.5

CTRL_REG4_G (23h)

8.6

CTRL_REG5_G (24h)

Table 29. CTRL_REG4_G register

BDU

BLE

FS1

FS0

ST1

ST0

SIM

Table 30. CTRL_REG4_G description

BDU

Block data update. Default value: 0

(0: continuous update; 1: output registers not updated until MSb and LSb

read)

BLE

Big/little endian data selection. Default value 0.

(0: Data LSb @ lower address; 1: Data MSb @ lower address)

FS1-FS0

Full-scale selection. Default value: 00

(00: 245 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)

ST1-ST0

Self-test enable. Default value: 00

(00: Self-test disabled; Other: See Table 31)

SIM

SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 31. Self-test mode configuration

ST1

ST0

Self-test mode

Normal mode

Self-test 0 (1)(X positive sign, Y and Z negative sign)

1. DST sign (absolute value in

Table 3)

10--

Self-test 1 (1) (X negative sign, Y and Z positive sign)

Table 32. CTRL_REG5_G register

BOOT

FIFO_EN

HPen

INT1_Sel1 INT1_Sel0

Out_Sel1

Out_Sel0

Table 33. CTRL_REG5_G description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO_EN

FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO enable)

HPen

High-pass filter enable. Default value: 0

(0: HPF disabled; 1: HPF enabled) (See Figure 18)

INT1_Sel1-INT1_Sel0

INT1 selection configuration. Default value: 00

(See Figure 18)

Out_Sel1-Out_Sel0

Out selection configuration. Default value: 00

(See Figure 18)

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