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EPF10K100 数据表(PDF) 56 Page - Altera Corporation |
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EPF10K100 数据表(HTML) 56 Page - Altera Corporation |
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56 / 128 page  56 Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industry- standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point- to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Figure 24 shows the overall timing model, which maps the possible paths to and from the various elements of the FLEX 10K device. Figure 24. FLEX 10K Device Timing Model Dedicated Clock/Input Interconnect I/O Element Logic Element Embedded Array Block |
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