EPF10K100 datasheet(17/128 Pages) ALTERA

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Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Cascade Chain

With the cascade chain, the FLEX 10K architecture can implement

functions that have a very wide fan-in. Adjacent LUTs can be used to

compute portions of the function in parallel; the cascade chain serially

connects the intermediate values. The cascade chain can use a logical AND

or logical OR (via De Morgan’s inversion) to connect the outputs of

adjacent LEs. Each additional LE provides four more inputs to the

effective width of a function, with a delay as low as 0.7 ns per LE. Cascade

chain logic can be created automatically by the Compiler during design

processing, or manually by the designer during design entry.

Cascade chains longer than eight bits are implemented automatically by

linking several LABs together. For easier routing, a long cascade chain

skips every other LAB in a row. A cascade chain longer than one LAB

skips either from even-numbered LAB to even-numbered LAB, or from

odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first

LAB in a row cascades to the first LE of the third LAB). The cascade chain

does not cross the center of the row (e.g., in the EPF10K50 device, the

cascade chain stops at the eighteenth LAB and a new one begins at the

nineteenth LAB). This break is due to the EAB’s placement in the middle

of the row.

Figure 8 shows how the cascade function can connect adjacent LEs to form

functions with a wide fan-in. These examples show functions of 4n

variables implemented with n LEs. The LE delay is as low as 1.6 ns; the

cascade chain delay is as low as 0.7 ns. With the cascade chain, 3.7 ns is

needed to decode a 16-bit address.

Figure 8. Cascade Chain Operation

LE1

LUT

LE2

LUT

d[3..0]

d[7..4]

d[(4

n-1)..(4n-4)]

d[3..0]

d[7..4]

d[(4

n-1)..(4n-4)]

LE1

LE2

LUT

AND Cascade Chain

OR Cascade Chain

EPF10K100 数据表(PDF) 17 Page - Altera Corporation

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