EPF10K100 datasheet(43/128 Pages) ALTERA

43 / 128 page

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 18 shows the timing requirements for the JTAG signals.

Figure 18. JTAG Waveforms

Table 16 shows the timing parameters and values for FLEX 10K devices.

Table 16. JTAG Timing Parameters & Values

Symbol

Parameter

Min

Max

Unit

tJCP

TCK

clock period

100

tJCH

TCK

clock high time

tJCL

TCK

clock low time

tJPSU

JTAG port setup time

tJPH

JTAG port hold time

tJPCO

JTAG port clock to output

tJPZX

JTAG port high impedance to valid output

tJPXZ

JTAG port valid output to high impedance

tJSSU

Capture register setup time

tJSH

Capture register hold time

tJSCO

Update register clock to output

tJSZX

Update register high-impedance to valid output

tJSXZ

Update register valid output to high impedance

TDO

TCK

tJPZX

JPCO

tJPH

t JPXZ

tJCP

tJPSU

t JCL

tJCH

TDI

TMS

Signal

to Be

Captured

Signal

to Be

Driven

JSZX

tJSSU

tJSH

JSCO

tJSXZ

EPF10K100 数据表(PDF) 43 Page - Altera Corporation

EPF10K100 数据表(HTML) 43 Page - Altera Corporation

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