EPF10K100 datasheet(24/128 Pages) ALTERA

24 / 128 page

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Asynchronous Preset

An asynchronous preset is implemented as either an asynchronous load,

or with an asynchronous clear. If DATA3 is tied to VCC, asserting

LABCTRL1

asynchronously loads a one into the register. Alternatively, the

Altera software can provide preset control by using the clear and

inverting the input and output of the register. Inversion control is

available for the inputs to both LEs and IOEs. Therefore, if a register is

preset by only one of the two LABCTRL signals, the DATA3 input is not

needed and can be used for one of the LE operating modes.

Asynchronous Preset & Clear

When implementing asynchronous clear and preset, LABCTRL1 controls

the preset and LABCTRL2 controls the clear. DATA3 is tied to VCC,

therefore, asserting LABCTRL1 asynchronously loads a one into the

Asynchronous Load with Clear

When implementing an asynchronous load in conjunction with the clear,

LABCTRL1

implements the asynchronous load of DATA3 by controlling

the register preset and clear. LABCTRL2 implements the clear by

controlling the register clear; LABCTRL2 does not have to feed the preset

circuits.

Asynchronous Load with Preset

When implementing an asynchronous load in conjunction with preset, the

Altera software provides preset control by using the clear and inverting

the input and output of the register. Asserting LABCTRL2 presets the

inverts the signal that drives DATA3 to account for the inversion of the

Asynchronous Load without Preset or Clear

When implementing an asynchronous load without preset or clear,

LABCTRL1

implements the asynchronous load of DATA3 by controlling

the register preset and clear.

EPF10K100 数据表(PDF) 24 Page - Altera Corporation