EPF10K100 datasheet(27/128 Pages) ALTERA

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Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

For improved routing, the row interconnect is comprised of a combination

of full-length and half-length channels. The full-length channels connect

to all LABs in a row; the half-length channels connect to the LABs in half

of the row. The EAB can be driven by the half-length channels in the left

half of the row and by the full-length channels. The EAB drives out to the

full-length channels. In addition to providing a predictable, row-wide

interconnect, this architecture provides increased routing resources. Two

neighboring LABs can be connected using a half-row channel, thereby

saving the other half of the channel for the other half of the row.

Table 7 summarizes the FastTrack Interconnect resources available in

each FLEX 10K device.

In addition to general-purpose I/O pins, FLEX 10K devices have six

dedicated input pins that provide low-skew signal distribution across the

device. These six inputs can be used for global clock, clear, preset, and

peripheral output enable and clock enable control signals. These signals

are available as control signals for all LABs and IOEs in the device.

The dedicated inputs can also be used as general-purpose data inputs

because they can feed the local interconnect of each LAB in the device.

However, the use of dedicated inputs as data inputs can introduce

additional delay into the control signal network.

Table 7. FLEX 10K FastTrack Interconnect Resources

Device

Rows

Channels per

Row

Columns

Channels per

Column

EPF10K10

EPF10K10A

144

EPF10K20

144

EPF10K30

EPF10K30A

216

EPF10K40

216

EPF10K50

EPF10K50V

216

EPF10K70

312

EPF10K100

EPF10K100A

312

EPF10K130V

312

EPF10K250A

456

EPF10K100 数据表(PDF) 27 Page - Altera Corporation

EPF10K100 数据表(HTML) 27 Page - Altera Corporation

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