EPF10K100 datasheet(37/128 Pages) ALTERA

37 / 128 page

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

ClockLock &

ClockBoost

Features

To support high-speed designs, selected FLEX 10K devices offer optional

ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)

that is used to increase design speed and reduce resource usage. The

ClockLock circuitry uses a synchronizing PLL that reduces the clock delay

and skew within a device. This reduction minimizes clock-to-output and

setup times while maintaining zero hold times. The ClockBoost circuitry,

which provides a clock multiplier, allows the designer to enhance device

area efficiency by sharing resources within the device. The ClockBoost

feature allows the designer to distribute a low-speed clock and multiply

that clock on-device. Combined, the ClockLock and ClockBoost features

provide significant improvements in system performance and

bandwidth.

The ClockLock and ClockBoost features in FLEX 10K devices are enabled

through the Altera software. External devices are not required to use these

features. The output of the ClockLock and ClockBoost circuits is not

available at any of the device pins.

The ClockLock and ClockBoost circuitry locks onto the rising edge of the

incoming clock. The circuit output can only drive the clock inputs of

registers; the generated clock cannot be gated or inverted.

The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and

ClockBoost circuitry. When the dedicated clock pin is driving the

ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.

In designs that require both a multiplied and non-multiplied clock, the

clock trace on the board can be connected to GCLK1. With the Altera

software, GCLK1 can feed both the ClockLock and ClockBoost circuitry in

the FLEX 10K device. However, when both circuits are used, the other

clock pin (GCLK0) cannot be used. Figure 17 shows a block diagram of

how to enable both the ClockLock and ClockBoost circuits in the Altera

software. The example shown is a schematic, but a similar approach

applies for designs created in AHDL, VHDL, and Verilog HDL. When the

ClockLock and ClockBoost circuits are used simultaneously, the input

frequency parameter must be the same for both circuits. In Figure 17, the

input frequency must meet the requirements specified when the

ClockBoost multiplication factor is two.

EPF10K100 数据表(PDF) 37 Page - Altera Corporation

EPF10K100 数据表(HTML) 37 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载