EPF10K100 datasheet(14/128 Pages) ALTERA

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Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Each LAB provides four control signals with programmable inversion

that can be used in all eight LEs. Two of these signals can be used as clocks;

the other two can be used for clear/preset control. The LAB clocks can be

driven by the dedicated clock input pins, global signals, I/O signals, or

internal signals via the LAB local interconnect. The LAB preset and clear

control signals can be driven by the global signals, I/O signals, or internal

signals via the LAB local interconnect. The global control signals are

typically used for global clock, clear, or preset signals because they

provide asynchronous control with very low skew across the device. If

logic is required on a control signal, it can be generated in one or more LEs

in any LAB and driven into the local interconnect of the target LAB. In

addition, the global control signals can be generated from LE outputs.

Logic Element

The LE, the smallest unit of logic in the FLEX 10K architecture, has a

compact size that provides efficient logic utilization. Each LE contains a

four-input LUT, which is a function generator that can quickly compute

any function of four variables. In addition, each LE contains a

programmable flipflop with a synchronous enable, a carry chain, and a

cascade chain. Each LE drives both the local and the FastTrack

Interconnect. See Figure 6.

Figure 6. FLEX 10K Logic Element

To LAB Local

Interconnect

Carry-In

Clock

Select

Carry-Out

Look-Up

Table

(LUT)

Clear/

Preset

Logic

Carry

Chain

Cascade

Chain

Cascade-In

Cascade-Out

To FastTrack

Interconnect

Programmable

PRN

CLRN

ENA

Chip-Wide

Reset

data1

data2

data3

data4

labctrl1

labctrl2

labctrl3

labctrl4

EPF10K100 数据表(PDF) 14 Page - Altera Corporation

EPF10K100 数据表(HTML) 14 Page - Altera Corporation

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