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EPF10K100 数据表(PDF) 30 Page - Altera Corporation |
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EPF10K100 数据表(HTML) 30 Page - Altera Corporation |
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30 / 128 page ![]() 30 Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 13. Bidirectional I/O Registers VCC OE[7..0] CLK[1..0] ENA[5..0] CLRN[1..0] Peripheral Control Bus CLRN DQ ENA VCC 2 Dedicated Clock Inputs Slew-Rate Control Open-Drain Output Chip-Wide Output Enable CLK[3..2] 2 12 VCC VCC Chip-Wide Reset 4 Dedicated Inputs Row and Column Interconnect 4 VCC CLRN DQ ENA Chip-Wide Reset CLRN DQ ENA Chip-Wide Reset VCC Input Register Output Register OE Register |
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