AD9852ASQZ datasheet(32/52 Pages) AD

32 / 52 page

AD9852

Rev. E | Page 32 of 52

Table 9. Register Layout1

AD9852 Register Layout

Parallel

Address

(Hex)

Serial

Address

(Hex)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Value

(Hex)

Phase Adjust Register 1 <13:8> (Bits 15, 14 don’t care)

Phase Adjust Register 1 <7:0>

Phase 1

Phase Adjust Register 2 <13:8> (Bits 15, 14 don’t care)

Phase Adjust Register 2 <7:0>

Phase 2

Frequency Tuning Word 1 <47:40>

Frequency Tuning Word 1 <39:32>

Frequency Tuning Word 1 <31:24>

Frequency Tuning Word 1 <23:16>

Frequency Tuning Word 1 <15:8>

Frequency Tuning Word 1 <7:0>

Frequency 1

Frequency Tuning Word 2 <47:40>

Frequency Tuning Word 2 <39:32>

Frequency Tuning Word 2 <31:24>

Frequency Tuning Word 2 <23:16>

Frequency Tuning Word 2 <15:8>

Frequency Tuning Word 2 <7:0>

Frequency 2

Delta frequency word <47:40>

Delta frequency word <39:32>

Delta frequency word <31:24>

Delta frequency word <23:16>

Delta frequency word <15:8>

Delta frequency word <7:0>

Update clock <31:24>

Update clock <23:16>

Update clock <15:8>

Update clock <7:0>

Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care)

Ramp rate clock <15:8>

Ramp rate clock <7:0>

Don’t care

CR [31]

Don’t care

Don’t

care

Comp

Reserved,

always

low

Control

DAC PD

DIG PD

Don’t care

PLL range

Bypass

PLL

Ref

Mult 4

Ref

Mult 3

Ref Mult 2

Ref

Mult 1

Ref Mult 0

CLR ACC1

CLR ACC2

Triangle

Don’t

care

Mode 2

Mode 1

Mode 0

Int/Ext

update clock

Don’t care

Bypass inv

sinc

OSK EN

OSK INT

Don’t care

LSB first

SDO active

CR [0]

Output shaped keying multiplier <11:8> (Bits 15, 14, 13, 12 don’t care)

Output shaped keying multiplier <7:0>

Don’t care

Output shaped keying ramp rate <7:0>

Control DAC <11:8> (Bits 15, 14, 13, 12 don’t care)

Control DAC <7:0> (Data is required to be in twos complement format)

1 The shaded sections comprise the control register.

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