AD9852ASQZ datasheet(28/52 Pages) AD

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AD9852

Rev. E | Page 28 of 52

The two fixed elements of the transition time are the period of

the system clock (which drives the ramp rate counter) and the

number of amplitude steps (4096). For example, if the system

clock of the AD9852 is 100 MHz (10 ns period) and the ramp

rate counter is programmed for a minimum count of 3, two system

clock periods are required: one rising edge loads the countdown

value, and the next edge decrements the counter from 3 to 2. If the

countdown value is less than 3, the ramp rate counter stalls and

therefore produces a constant scaling value to the digital multiplier.

This stall condition may have an application for the user.

The relationship of the 8-bit countdown value to the time between

output pulses is given as

(N + 1) × System Clock Period

where N is the 8-bit countdown value.

A total of 4096 output pulses is required to advance the 12-bit

up-counter from zero scale to full scale. Therefore, the minimum

output shaped keying ramp time for a 100 MHz system clock is

4096 × 4 × 10 ns ≈ 164 μs

The maximum ramp time is

4096 × 256 × 10 ns ≈ 10.5 ms

Finally, by changing the logic state of Pin 30, output shaped

keying automatically performs the programmed output envelope

functions when OSK INT is high. A logic high on Pin 30 causes

the outputs to linearly ramp up to full-scale amplitude and hold

until the logic level is changed to low, causing the outputs to

ramp down to zero scale.

12-BIT DIGITAL

MULTIPLIER

(BYPASS MULTIPLIER)

OSK EN = 0

OSK EN = 1

OSK EN = 0

OSK EN = 1

DIGITAL

SIGNAL IN

USER-PROGRAMMABLE

12-BIT MULTIPLIER

OUTPUT SHAPED

KEYING MULTIPLIER

OSK INT = 1

OSK INT = 0

8-BIT RAMP

RATE

COUNTER

SYSTEM

CLOCK

ON/OFF OUTPUT SHAPED

KEYING PIN

12-BIT

UP/DOWN

COUNTER

DDS DIGITAL

OUTPUT

COSINE

DAC

Figure 47. Block Diagram of the Digital Multiplier Section Responsible for the Output Shaped Keying Function

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