AD9852ASQZ datasheet(20/52 Pages) AD

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AD9852

Rev. E | Page 20 of 52

I/O UD CLK

FREQUENCY

MODE

TW1

TW2

010 (RAMPED FSK)

000 (DEFAULT)

REQUIRES A POSITIVE TWOS COMPLEMENT VALUE

RAMP RATE

DFW

FSK DATA (PIN 29)

Figure 34. Ramped FSK Mode (Start at F1)

FREQUENCY

MODE

TW1

TW2

FSK DATA (PIN 29)

010 (RAMPED FSK)

000 (DEFAULT)

I/O UD CLK

Figure 35. Ramped FSK Mode (Start at F2)

The purpose of ramped FSK is to provide better bandwidth

containment than can be achieved using traditional FSK. In

ramped FSK, the instantaneous frequency changes of traditional

FSK are replaced with more gradual, user-defined frequency

changes. The dwell time at F1 and F2 can be equal to or much

greater than the time spent at each intermediate frequency. The

user controls the dwell time at F1 and F2, the number of

intermediate frequencies, and the time spent at each frequency.

Unlike unramped FSK, ramped FSK requires the lowest

frequency to be loaded into the F1 registers and the highest

frequency to be loaded into the F2 registers.

Several registers must be programmed to instruct the DDS

regarding the resolution of intermediate frequency steps (48 bits)

and the time spent at each step (20 bits). Furthermore, the CLR

ACC1 bit in the control register should be toggled (low-high-low)

prior to operation to ensure that the frequency accumulator is

starting from an all 0s output condition.

For piecewise, nonlinear frequency transitions, it is necessary

to reprogram the registers while the frequency transition is in

progress to affect the desired response.

Parallel Register Address 1A hex to Parallel Register Address 1C

hex comprise the 20-bit ramp rate clock registers. This is a

countdown counter that outputs a single pulse whenever the

count reaches 0. The counter is activated any time a logic level

change occurs on the FSK input (Pin 29). This counter is run at

the system clock rate, 300 MHz maximum. The time period

between each output pulse is

(N + 1) × System Clock Period

where N is the 20-bit ramp rate clock value programmed by

the user.

The allowable range of N is from 1 to (220 − 1). The output of

this counter clocks the 48-bit frequency accumulator shown in

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