AD9852ASQZ datasheet(34/52 Pages) AD

34 / 52 page

AD9852

Rev. E | Page 34 of 52

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases of a serial communication cycle with the

AD9852. Phase 1 is the instruction cycle, which is the writing of

an instruction byte into the AD9852 coincident with the first

eight SCLK rising edges. The instruction byte provides the

AD9852 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication

cycle. The Phase 1 instruction byte defines whether the next

data transfer is a read or write and the register address to be

acted upon.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9852. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9852

and the system controller. The number of data bytes transferred

during Phase 2 of the communication cycle is a function of the

expects every byte of the register being accessed to be

transferred. Table 11 describes how many bytes must be

transferred.

Table 11. Register Address vs. Data Bytes Transferred

Serial

Address

Number

of Bytes

Transferred

Phase Offset Tuning Word Register 1

Phase Offset Tuning Word Register 2

Frequency Tuning Word 1

Frequency Tuning Word 2

Delta frequency register

Update clock rate register

Ramp rate clock register

Control register

Digital multiplier register

On/off output shaped keying ramp

rate register

Control DAC register

At the completion of a communication cycle, the AD9852 serial

port controller expects the subsequent eight rising SCLK edges

to be the instruction byte of the next communication cycle. In

addition, an active high input on the IO RESET pin immediately

terminates the current communication cycle. After IO RESET

returns low, the AD9852 serial port controller requires the sub-

sequent eight rising SCLK edges to be the instruction byte of

the next communication cycle.

All data input to the AD9852 is registered on the rising edge of

SCLK, and all data is driven out of the AD9852 on the falling

edge of SCLK.

Figure 51 and Figure 52 are useful in understanding the general

operation of the AD9852 serial port.

INSTRUCTION

CYCLE

DATA TRANSFER

INSTRUCTION

BYTE

DATA BYTE 1

DATA BYTE 2

DATA BYTE 3

SDIO

Figure 51. Using SDIO as a Read/Write Transfer

INSTRUCTION

CYCLE

DATA TRANSFER

INSTRUCTION

BYTE

SDIO

DATA TRANSFER

DATA BYTE 1

DATA BYTE 2

DATA BYTE 3

SDO

Figure 52. Using SDIO as an Input and SDO as an Output

INSTRUCTION BYTE

The instruction byte contains the following information:

MSB

LSB

R/W

R/W—Bit 7 of the instruction byte determines whether a read

or write data transfer occurs following the instruction byte.

Logic high indicates that a read operation will occur. Logic 0

indicates that a write operation will occur.

Bit 6, Bit 5, and Bit 4 of the instruction byte are dummy bits

(don’t care).

A3, A2, A1, A0—Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction

byte determine which register is accessed during the data transfer

portion of the communication cycle (see Table 9 for register

address details).

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