AD9852ASQZ datasheet(33/52 Pages) AD

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AD9852

Rev. E | Page 33 of 52

A<5:0>

D<7:0>

tRDHOZ

tRDLOV

tAHD

tADV

SPECIFICATION

tADV

tAHD

tRDLOV

tRDHOZ

VALUE

15ns

5ns

15ns

10ns

DESCRIPTION

ADDRESS TO DATA VALID TIME (MAXIMUM)

ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)

RD LOW TO OUTPUT VALID (MAXIMUM)

RD HIGH TO DATA THREE-STATE (MAXIMUM)

Figure 49. Parallel Port Read Timing Diagram

D<7:0>

SPECIFICATION

tASU

tDSU

tADH

tDHD

tWRLOW

tWRHIGH

tWR

VALUE

8.0ns

3.0ns

0ns

2.5ns

7ns

10.5ns

DESCRIPTION

ADDRESS SETUP TIME TO WR SIGNAL ACTIVE

DATA SETUP TIME TO WR SIGNAL ACTIVE

ADDRESS HOLD TIME TO WR SIGNAL INACTIVE

DATA HOLD TIME TO WR SIGNAL INACTIVE

WR SIGNAL MINIMUM LOW TIME

WR SIGNAL MINIMUM HIGH TIME

MINIMUM WRITE TIME

tWR

A<5:0>

tASU

tAHD

tWRHIGH

tWRLOW

tDHD

tDSU

Figure 50. Parallel Port Write Timing Diagram

Table 10. Serial I/O Pin Requirements

Pin Number

Mnemonic

Serial I/O Description

1 to 8

D [7:0]

The parallel data pins are not active; tie these pins to VDD or GND.

14 to 16

A [5:3]

The A5, A4, and A3 parallel address pins are not active; tie these pins to VDD or GND.

A2/IO RESET

IO RESET.

A1/SDO

SDO.

A0/SDIO

SDIO.

I/O UD CLK

Update Clock. Same functionality for serial mode as parallel mode.

WR/SCLK

SCLK.

RD/CS

CS—Chip Select.

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