ICS1889 datasheet(14/35 Pages) ICST

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ICS1889

Extended Control Register (register 16)

The Extended Control Register is a 16-bit read write register

used to pre-program the ICS1889. At power-up and reset, this

subsequently be read or written. If written, the result is bit

dependent as discussed below.

Command Register Override (bit 15)

If set to a logic one, this bit allows a subsequent write to the

Status Register (register 1) and the PHY identifier registers 2

and 3. The contents of registers 2 and 3 may be set to any

value. The Status Register may have certain specified bits set

or reset. The first write to registers 1, 2 or 3 after this bit is set

will reset it preventing subsequent writes from having any

effect.

Reserved (bit 14)

This bit is reserved for ICS use. It must always be written with

a logic zero. The value of this bit when read is unspecified and

may be a logic zero or one.

Reserved (bit 13)

This bit is reserved for ICS use. It must always be written with

a logic zero. The value of this bit, when read, is unspecified

and may be a logic zero or one.

Extended Control Register (register 16)

BIT

Definition

When bit = 0

When bit = 1

Access

Default

Command Register Override Don’t allow write

Allow write

Reserved for ICS

Write logic zero. Read unspecified.

RW/0

—

Reserved for ICS

Write logic zero. Read unspecified.

RW/0

—

Reserved for ICS

Write logic zero. Read unspecified.

RW/0

—

Reserved for ICS

Write logic zero. Read unspecified.

RW/0

—

PHY address - S4

P4RD

PHY address - S3

MII management

P3TD

PHY address - S2

P2LI

PHY address - S1

0 - 31 Read Only

P1CL

PHY address - S0

P0FD

Reserved for ICS

Write logic zero. Read unspecified.

RW/0

—

Far End Fault

Disabled

Enabled

Transmit Far End Fault

No fault transmitted

Fault transmitted

Invalid Error Code Test

Disabled

Enabled

Reserved for ICS

Write logic zero. Read unspecified.

RW/0

—

Reserved for ICS

Write logic zero. Read unspecified.

RW/0

—

Reserved (bit 12)

This bit is reserved for ICS use. It must always be written with

a logic zero. The value of this bit when read is unspecified and

may be a logic zero or one.

Reserved (bit 11)

This bit is reserved for ICS use. It must always be written with

a logic zero. The value of this bit when read is unspecified and

may be a logic zero or one.

PHY Address (Bits 10 through 6)

These 5 bits are used to indicate the address of the ICS1889

on the management port of the MII (any number in the range

0 - 31). A read returns the address. Extra care should be taken

if a command override write is performed on these bits, as a

change in the PHY address must be accounted for by the

device reading and writing to the MII Management interface.

Reserved (bit 5)

This bit is reserved for ICS use. It must always be written with

a logic zero. The value of this bit when read is unspecified and

may be a logic zero or one.

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