ICS1889 datasheet(17/35 Pages) ICST

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ICS1889

Data Rate (bit 15)

This bit is permanently set to a logic one indicating it only

operates at 100 Mbps.

Duplex (bit 14)

If set to a logic one, this bit indicates that the full duplex mode

has been selected. If set to a logic zero, it indicates that the

half duplex mode has been selected. It is initialized to logic

zero.

Reserved (bit 13)

This bit is reserved for ICS use. The value of this bit is

unspecified and may be a logic zero or one.

Reserved (bit 12)

This bit is reserved for ICS use. The value of this bit is

unspecified and may be a logic zero or one.

Reserved (bit 11)

This bit is reserved for ICS use. The value of this bit is

unspecified and may be a logic zero or one.

Receive Signal Error (bit 10)

If set to a logic one, the Receive Signal error bit indicates that

the ICS1889 read channel has at some point been unable to

detect the receive channel signal. This bit will remain set until

cleared by reading the contents of register 17. It is initialized

to logic zero.

PLL Lock Error (bit 9)

If set to a logic one, the loss of PLL lock (bit 9) indicates that

the ICS1889 read channel PLL has failed to lock on to the

read channel signal. This bit will remain set until cleared by

reading the contents of register 17. It is initialized to logic

zero.

False Carrier (bit 8)

If set to a logic one, the false carrier (bit 8) indicates that the

ICS1889 has detected a false carrier sometime since this bit

was last reset. This bit will remain set until cleared by reading

the contents of register 17. It is initialized to logic zero.

Invalid Symbol (bit 7)

If set to a logic one, the invalid symbol (bit 7) indicates that an

invalid symbol has been detected in a received frame since the

bit was last reset. This bit will remain set until cleared by

reading the contents of register 17. It is initialized to logic

zero.

Halt Symbol (bit 6)

If set to a logic one, the halt symbol (bit 6) indicates that the

ICS1889 has detected the halt symbol in a frame since bit 11

was last reset. This bit will remain set until cleared by reading

the contents of register 17. It is initialized to logic zero.

Premature End (bit 5)

This bit is normally a logic zero indicating normal data

streams. If two IDLE symbols are detected during the

reception of a receive data stream, this bit is set to a logic one

and the ICS1889 returns to the idle state This bit is initialized

to a logic zero.

Reserved (bit 4)

This bit is reserved for ICS use. The value of this bit is

unspecified and may be a logic zero or one.

Reserved (bit 3)

This bit is reserved for ICS use. The value of this bit is

unspecified and may be a logic zero or one.

Priority Pin State (bit 2)

This bit reflects the setting of the Priority Pin (pin 17). When

this bit is a logic zero, duplex mode is controlled by the

Duplex Enable pin (pin 18). When this bit is a logic one,

duplex mode is controlled by the Duplex Mode bit (0:8).

Remote Fault (bit 1)

This is a copy of the Remote Fault bit of the Status Register

(register 1).

Link Status (bit 0)

This is a copy of the Link Status bit of the Status Register

(register 1).

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