ICS1889 datasheet(19/35 Pages) ICST

19 / 35 page

ICS1889

Transmit Data 0 TXD0

Transmit Data 0 (TXD0) is the least significant bit of the

transmit data nibble. TXD0 is sampled by the ICS1889

synchronously with the Transmit Data Clock when TXEN is

asserted. When TXEN is de-asserted the ICS1889 is

unaffected by the state of TXD0.

Transmit Error TXER

The assertion ofTransmit Error (TXER) for one or more clock

periods will cause the ICS1889 to emit one or more HALT

symbols. The signal is synchronous with TXCLK. In the

normal operating mode, a HALT symbol will be substituted

for the next nibble encoded. If the invalid error code test bit in

the Configuration Register is set (register 16, bit 2), TXER

becomes an additional input to the 4B5B encoder. This allows

the ICS1889 to send the full set of 32 symbols including the

invalid symbols. Table 1 shows the modified 4B5B encoding

in the test mode. A timing diagram for TXER is shown in

Figure xxx.

Receive Clock RXCLK

The Receive Clock (RXCLK) is sourced by the ICS1889.

There are two possible sources for the Receive Clock

(RXCLK). When a carrier is present on the receive pair, the

source is the recovered clock from the data stream. When no

carrier is present on the receive pair, the source is

synchronized to the transmit PLL. The IDLE symbol is sent

during periods of inactivity and the Recovered clock will be

selected.

The ICS1889 will only switch between clock sources when

Receive Data Valid (RXDV) is de-asserted. During the period

between Carrier Sense (CRS) being asserted and Receive

Data Valid being asserted, a clock phase change of up to 360

degrees may occur. Following the de-assertion of Receive

Data Valid a clock phase of 360 degrees may occur.

When Receive Data Valid is asserted, the Receive Clock

frequency is 25% of the data rate, 25 MHz. The minimum low

and high times of the clock are guaranteed to be 35% under all

conditions and the duty cycle between 35% and 65% except

during the clock transition conditions specified above. The

ICS1889 synchronizes Receive Data Valid, Received Data

and Receive Error with Receive Clock (RXCLK).

Receive Data Valid RXDV

Receive Data Valid (RXDV) is generated by the ICS1889. It

indicates that the ICS1889 is recovering and decoding data

nibbles on the Receive Data (RXD) data lines synchronous

with the Receive Data Clock (RXCLK). It is the responsibility

of the MAC to assemble nibbles into MAC frames since the

ICS1889 has no knowledge of the frame structure and is

merely a nibble processor. The ICS1889 asserts RXDV

when it detects a start of stream delimiter (SSD) and de-

asserts it following the last data nibble or upon detection of a

signal error. RXDV is synchronous with the Receive Data

Clock (RXCLK).

Receive Data RXD3

Receive Data 3 (RXD3) is the most significant bit of the

receive data nibble. RXD is sourced by the ICS1889. When

Receive Data Valid (RXDV) is asserted by the ICS1889, it

will transfer the fourth bit of the symbol synchronously with

Receive Clock (RXCLK).

Receive Data RXD2

Receive Data 2 (RXD2) is sourced by the ICS1889. When

Receive Data Valid (RXDV) is asserted by the ICS1889, it

will transfer the third bit of the symbol synchronously with

Receive Clock (RXCLK).

Receive Data RXD1

Receive Data 1 (RXD1) is sourced by the ICS1889. When

Receive Data Valid (RXDV) is asserted by the ICS1889, it

will transfer the second bit of the symbol synchronously with

Receive Clock (RXCLK).

Receive Data RXD0

Receive Data 0 (RXD0) is the least significant bit of the

receive data nibble. RXD0 is sourced by the ICS1889. When

Receive Data Valid (RXDV) is asserted by the ICS1889, it

will transfer the first bit of the symbol synchronously with

Receive Clock (RXCLK).

ICS1889 数据表(PDF) 19 Page - Integrated Circuit Systems

ICS1889 数据表(HTML) 19 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

数据表下载

链接网址

ICS1889 数据表(PDF) 19 Page - Integrated Circuit Systems

ICS1889 数据表(HTML) 19 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

数据表 下载

链接网址

数据表下载