ICS1889 datasheet(5/35 Pages) ICST

5 / 35 page

ICS1889

4B/5B Encoder/Decoder

The ICS1889 uses a 4B5B coding scheme. This maps a 4-bit

nibble to a 5-bit code group called a symbol. Five bits allow

32 possible symbols, 16 are used for data encoding, 6 are used

for control and 10 are not used and are invalid. The control

symbols used are JK as the SSD, TR as the ESD, I as

the IDLE symbol and H to signal an error. All other

symbols are invalid and, if detected, will set the receive error

bit in the status register, and cause the RXER signal to be

asserted (see Table 1 below).

When transmitting, nibbles from the MII are converted to a 5-

bit code groups. During transmission, the first 16 nibbles

obtained from the MII are the MAC frame preamble.

The ICS1889 replaces the first two nibbles with the start-of-

stream delimiter (the JK symbol pair). Following the last

nibble, the ICS1889 adds the end-of-stream delimiter (the

TR symbol pair).

When receiving, 5-bit code groups are converted to nibbles

and presented to the MII. If the ICS1889 detects one or more

invalid symbols, it sets the Invalid Symbol bit (17:7) in the

QuickPoll Status Register. When receiving a frame, the first

two 5-bit code groups received are the start-of-stream

delimiter (the JK symbol pair), the ICS1889 strips them

and substitutes two nibbles of the normal preamble pattern.

The last two 5-bit code groups are the end-of-stream delimiter

(the TR symbol pair), these are stripped from the nibbles

presented to the MAC.

1. The IDLE symbol is sent continuously between frames.

2. J and K are the SSD and are always sent in pairs.

3. K always follows J.

4. T and R are the ESD and are always sent in pairs.

5. R always follows T.

6. A HALT symbol is used to signal an error condition.

Table 1: 4B5B Encoding

Symbol

Meaning

4B Code

3 2 1 0

5B Code

4 3 2 1 0

Symbol

Meaning

4B Code

3 2 1 0

5B Code

4 3 2 1 0

Data 0

0 0 0 0

1 1 1 1 0

Data 8

1 0 0 0

1 0 0 1 0

Data 1

0 0 0 1

0 1 0 0 1

Data 9

1 0 0 1

1 0 0 1 1

Data 2

0 0 1 0

1 0 1 0 0

Data A

1 0 1 0

1 0 1 1 0

Data 3

0 0 1 1

1 0 1 0 1

Data B

1 0 1 1

1 0 1 1 1

Data 4

0 1 0 0

0 1 0 1 0

Data C

1 1 0 0

1 1 0 1 0

Data 5

0 1 0 1

0 1 0 1 1

Data D

1 1 0 1

1 1 0 1 1

Data 6

0 1 1 0

0 1 1 1 0

Data E

1 1 1 0

1 1 1 0 0

Data 7

0 1 1 1

0 1 1 1 1

Data F

1 1 1 1

1 1 1 0 1

Idle

Undefined

1 1 1 1 1

Invalid

Undefined

0 0 0 1 0

SSD

0 1 0 1

1 1 0 0 0

Invalid

Undefined

0 0 0 1 1

SSD

0 1 0 1

1 0 0 0 1

Invalid

Undefined

0 0 1 0 1

ESD

Undefined

0 1 1 0 1

Invalid

Undefined

0 0 1 1 0

ESD

Undefined

0 0 1 1 1

Invalid

Undefined

0 1 0 0 0

Error

Undefined

0 0 1 0 0

Invalid

Undefined

0 1 1 0 0

Invalid

Undefined

0 0 0 0 0

Invalid

Undefined

1 0 0 0 0

Invalid

Undefined

0 0 0 0 1

Invalid

Undefined

1 1 0 0 1

Invalid Error Code Test

TXER asserted

Idle

1 1 1 1

1 1 1 1 1

Invalid

0 0 1 0

0 0 0 1 0

SSD

1 1 1 0

1 1 0 0 0

Invalid

0 0 1 1

0 0 0 1 1

SSD

1 0 1 1

1 0 0 0 1

Invalid

0 1 0 1

0 0 1 0 1

ESD

1 0 0 1

0 1 1 0 1

Invalid

0 1 1 0

0 0 1 1 0

ESD

0 1 1 1

0 0 1 1 1

Invalid

1 0 0 0

0 1 0 0 0

Error

0 1 0 0

0 0 1 0 0

Invalid

1 0 1 0

0 1 1 0 0

Invalid

0 0 0 0

0 0 0 0 0

Invalid

1 1 0 0

1 0 0 0 0

Invalid

0 0 0 1

0 0 0 0 1

Invalid

1 1 0 1

1 1 0 0 1

ICS1889 数据表(PDF) 5 Page - Integrated Circuit Systems

ICS1889 数据表(HTML) 5 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

数据表下载

链接网址

ICS1889 数据表(PDF) 5 Page - Integrated Circuit Systems

ICS1889 数据表(HTML) 5 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

数据表 下载

链接网址

数据表下载