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ICS1889 数据表(PDF) 16 Page - Integrated Circuit Systems |
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ICS1889 数据表(HTML) 16 Page - Integrated Circuit Systems |
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16 / 35 page  16 ICS1889 QuickPoll Status Register (register 17) The QuickPoll status register is a 16-bit read only register used to indicate the comprehensive status of the ICS1889. All register status bits that might need to be repetitively examined at run time are located in this register, even though some bits duplicate functionality from other registers. This allows the device status to be rapidly obtained with a single register access. The register is accessed via the management interface of the MII. It can always be read and may be written by setting the override bit in the Configuration Register (register 16, bit 15) and then performing a write operation. It is initialized during a power-up or reset to predefined default values. QuickPoll Status Register (register 17) BIT Definition When bit = 0 When bit = 1 Access Default 15 Data Rate Always a logic one 100 Mbps selected RO 1 14 Duplex Half duplex selected Full duplex selected RO 0 if PRIO=1 or DPEN if PRIO=0 13 Reserved for ICS Read unspecified RO — 12 Reserved for ICS Read unspecified RO — 11 Reserved for ICS Read unspecified RO — 10 Receive Signal Error Signal Loss of signal RO/LH 0 9 PLL Lock Error PLL locked PLL failed to lock RO/LH 0 8 False Carrier Detect Normal carrier or idle False carrier detected RO/LH 0 7 Invalid Symbol Valid symbols Invalid symbol detected RO/LH 0 6 Halt Symbol Normal symbols HALT symbol detected RO/LH 0 5 Premature End Normal stream Stream with two IDLES RO/LH 0 4 Reserved for ICS Read unspecified RO — 3 Reserved for ICS Read unspecified RO — 2 Priority Pin State Hardware Software RO PRIO 1 Remote Fault No remote fault detected Remote fault detected RO/LH 0 0 Link Status Link is not valid Link is valid RO/LL 0 |
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