ICS1889 datasheet(8/35 Pages) ICST

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ICS1889

Control Register (register 0)

The control register is a 16-bit read/write register used to set

the basic configuration modes of the ICS1889. It is accessed

through the management interface of the MII.

Reset (bit 15) default = 0

Setting this bit to a logic 1 will result in the ICS1889 setting

all its status and control registers to their default values.

During this process the ICS1889 may change internal states

and the states of physical links attached to it. While in process,

the bit will remain set and no other write commands to the

control register will be accepted. The reset process will be

completed within 500 ms and the bit will be cleared indicating

that the reset process is complete.

Loop Back (bit 14)

Setting this bit to a logic one causes the ICS1889 to tristate

the transmit circuitry from sending data and the receive

circuitry from receiving data. The collision detection circuitry

is also disabled unless the collision test command bit is set.

Data presented to the MII transmit data path is returned to the

MII receive data path (see ICS1889 Block Diagram, page 2).

Data Rate (bit 13)

This bit is permanently set to a logic one indicating that only

the 100 Mbps mode is supported.

Auto-Negotiation Enable (bit 12)

This feature is not available with fiber optic solutions. This bit

is permanently set to a logic zero indicating that it is not

supported.

Power-Down (bit 11)

Setting it to logic one will cause the ICS1889 to isolate its

transmit data output and its MII interface with the exception

of the management interface. The ICS1889 will then enter a

power-down mode where only the management interface and

logic remain active. Setting this bit to logic zero after it has

been set to a logic one will cause the ICS1889 to power-up its

logic and then reset all error conditions. It then enables

transmit data and the MII interface. This process takes 500 ms

to complete.

Control Register (register 0)

BIT

Function

Effect when bit = 0

Effect when bit = 1

Access

Default

Reset

No Effect

Reset PHY

RW/SC

Loop Back

Disable loop back mode

Enable loop back mode

Data Rate

Always set to a logic one 100 Mpbs operation

Auto-Negotiate Enable

No Effect

Always set to logic zero

Power-Down

Normal Mode

Reduced

power consumption

Isolate

No Effect

Isolate PHY from MII

0 if PHY

Address

< >0,

1 if PHY

Address=0

Restart Auto-Negotitation No Effect

Always set to logic zero

Duplex Mode

Half Duplex

Full Duplex

Collision Test

No Effect

Enable collision signal test

Reserved

If read, bits 0-6 and bits 9 and 12 will return logic

zeroes and bit 13 will return a logic one.

Reserved

Writes to these bits will have no effect.

Reserved

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