ICS1889 datasheet(7/35 Pages) ICST

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ICS1889

Management Interface

The ICS1889 provides a management interface to connect to

a management entity. The two wire serial interface is part of

the MII and is described in the MII section. The interface

allows the transport of status information from the ICS1889

to the management entity and the transport of command

words to the ICS1889. It includes a register set, a frame

format, and a protocol.

Management Register Set

The register set includes the mandatory basic control and

status registers and an extended set. The ICS1889 implements

the following registers.

Control

(register 0)

Status

(register 1)

PHY Identifier

(register 2)

PHY Identifier

(register 3)

Extended Control

(register 16)

QuickPoll Status

(register 17)

Management Frame Structure

The management interface uses a serial bit stream with a

specified frame structure and protocol as defined below.

Preamble

11...11

(32 ones)

SOF

Op Code

10 (read), 01 (write)

Address

AAAAA

(5 bits)

RRRRR

(5 bits)

(2 bits)

Data

DD...DD

(16 bits)

Idle

high impedance

Preamble

The ICS1889 looks for a pattern of 32 logic ones followed by

the SOF delimiter before responding to a transaction.

Start of Frame

Following the preamble a start of frame delimiter of zero-one

initiates a transaction.

Operation Code

The valid codes are 10 for a read operation and 01 for a write

operation. Other codes are ignored.

Address

There may be up to 32 PHYs attached to the MII. This 5 bit

address is compared to the internal address of the ICS1889, as

set by the P[0...4]* pins, for a match.

The ICS1889 uses this field to select one of the registers

within the set. If a nonexistent register is specified, the

ICS1889 ignores the command.

This 2-bit field is used by the ICS1889 to avoid contention

during read transactions. When writing to the ICS1889, the

TA bits should be set to 10. When reading from the ICS1889,

the device will tristate during this time.

Data

This is a 16-bit field with bit 15 being the first bit sent or

received.

Idle

The ICS1889 is in the high impedance state during the idle

condition.

Read Only, writes ignored

Command Override Writable

RW/0

Read/Write only logic zero

Read/Write

Four types of register access are supported by the device.

Read Only (RO) bits may be read, but writes are ignored.

Command Override Writable (CW) bits may be read, but

writes are ignored unless preceded by writing a logic one to

the Command Register Override bit (16:15). Read Write Zero

(RW/0) bits may be read, but must only be written with a logic

zero value. Writing a logic one to this type of bit may prevent

the device from operating normally. Read Write (RW) bits

may be read and may be written to any value.

Default Values

No default value

Default to logic zero

Default to logic one

Default depends on the state of

the named pin

Modifier

Self Clearing

Latching Low

Latching High

Self clearing bits will clear without any further writes after a

specified amount of time. Latching bits are used to capture an

event. To obtain the current status of a latching bit, the bit

must be read twice in succession. If the special condition still

persists, the bit will be the same on the second read;

otherwise, the condition indication will not be present.

ICS1889 数据表(PDF) 7 Page - Integrated Circuit Systems

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