PM0214 datasheet(73/245 Pages) STMICROELECTRONICS

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PM0214

The STM32 Cortex-M4 instruction set

244

; sum of R5 and two times R1, sign extended it

; to a word value and put it in R0

STR R0, [R1, R2, LSL #2]; stores R0 to an address equal to sum of R1

; and four times R2

3.4.4

LDR and STR, unprivileged

Load and store with unprivileged access.

Syntax

op{type}T{cond} Rt, [Rn {, #offset}]; immediate offset

where:

•

‘op’ is either LDR (load register) or STR (store register)

•

‘type’ is one of the following:

B: Unsigned byte, zero extends to 32 bits on loads

SB: Signed byte, sign extends to 32 bits (LDR only)

H: Unsigned halfword, zero extends to 32 bits on loads

SH: Signed halfword, sign extends to 32 bits (LDR only)

—: Omit, for word

•

‘cond’ is an optional condition code (see Conditional execution on page 64)

•

‘Rt’ is the register to load or store

•

‘Rn’ is the register on which the memory address is based

•

‘offset’ is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the

value in Rn.

Operation

These load and store instructions perform the same function as the memory access

instructions with immediate offset (see LDR and STR, immediate offset on page 70). The

difference is that these instructions have only unprivileged access even when used in

privileged software.

When used in unprivileged software, these instructions behave in exactly the same way as

normal memory access instructions with immediate offset.

Restrictions

In these instructions:

•

Rn must not be PC

•

Rt must be neither SP nor PC.

Condition flags

These instructions do not change the flags.

Examples

STRBTEQ R4, [R7]

; conditionally store least significant byte in

; R4 to an address in R7, with unprivileged access

LDRHT R2, [R2, #8]; load halfword value from an address equal to

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