PM0214 datasheet(25/245 Pages) STMICROELECTRONICS

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PM0214

The Cortex-M4 processor

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Handler mode always uses the MSP, so the processor ignores explicit writes to the active

stack pointer bit of the CONTROL register when in Handler mode. The exception entry and

return mechanisms update the CONTROL register.

In an OS environment, it is recommended that threads running in Thread mode use the

process stack and the kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to

the PSP, either:

•

use the MSR instruction to set the Active stack pointer bit to 1, see MSR on page 174.

•

perform an exception return to Thread mode with the appropriate EXC_RETURN

value, see Exception return behavior on page 43.

When changing the stack pointer, software must use an ISB instruction immediately after

the MSR instruction. This ensures that instructions after the ISB execute using the new

stack pointer. See ISB on page 173

2.1.4

Exceptions and interrupts

The Cortex-M4 processor supports interrupts and system exceptions. The processor and

the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An

exception changes the normal flow of software control. The processor uses handler mode to

handle all exceptions except for reset. See Exception entry on page 41 and Exception

return on page 43 for more information.

The NVIC registers control interrupt handling. See Nested vectored interrupt controller

(NVIC) on page 193 for more information.

2.1.5

Data types

The processor:

•

Supports the following data types:

–

32-bit words

–

16-bit halfwords

–8-bit bytes

•

manages all memory accesses as little-endian. See Memory regions, types and

attributes on page 28 for more information.

2.1.6

The Cortex microcontroller software interface standard (CMSIS)

For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface

Standard (CMSIS) defines:

•

A common way to:

–

Access peripheral registers

–

Define exception vectors

•

The names of:

–

The registers of the core peripherals

–

The core exception vectors

•

A device-independent interface for RTOS kernels, including a debug channel

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