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PM0214

The Cortex-M4 processor

244

2.2.3

Behavior of memory accesses

The behavior of accesses to each region in the memory map is:

The Code, SRAM, and external RAM regions can hold programs. However, it is

recommended that programs always use the Code region. This is because the processor

has separate buses that enable instruction fetches and data accesses to occur

simultaneously.

The MPU can override the default memory access behavior described in this section. For

more information, see Memory protection unit (MPU) on page 178.

Instruction prefetch and branch prediction

The Cortex-M4 processor:

•

Prefetches instructions ahead of execution

•

Speculatively prefetches from branch target addresses.

Table 13. Memory access behavior

Address

range

Memory

region

Memory

type

Description

0x00000000-

0x1FFFFFFF

Code

Normal(1)

1. See Memory regions, types and attributes on page 28 for more information.

Executable region for program code. Can also put

data here.

0x20000000-

0x3FFFFFFF

SRAM

Normal(1) -

Executable region for data. Can also put code

here.

This region includes bit band and bit band alias

areas, see Table 14 on page 31.

0x40000000-

0x5FFFFFFF

Peripheral

Device(1)

XN(1)

This region includes bit band and bit band alias

areas, see Table 15 on page 31.

0x60000000-

0x9FFFFFFF

External

RAM

Normal(1) -

Executable region for data.

0xA0000000-

0xDFFFFFFF

External

device

Device(1)

XN(1) External Device memory

0xED000000-

0xED0FFFFF

Private

Peripheral

Bus

Strongly-

ordered(1)

XN(1)

This region includes the NVIC, System timer, and

system control block.

0xED100000-

0xFFFFFFFF

Memory

mapped

peripherals

Device(1)

XN(1)

This region includes all the STM32 standard

peripherals.

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