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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PM0214 数据表(PDF) 49 Page - STMicroelectronics |
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PM0214 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 245 page  DocID022708 Rev 4 49/245 PM0214 The STM32 Cortex-M4 instruction set 244 3 The STM32 Cortex-M4 instruction set This chapter is the reference material for the Cortex-M4 instruction set description in a User Guide. The following sections give general information: Section 3.1: Instruction set summary on page 49 Section 3.2: CMSIS intrinsic functions on page 57 Section 3.3: About the instruction descriptions on page 59 Each of the following sections describes a functional group of Cortex-M4 instructions. Together they describe all the instructions supported by the Cortex-M4 processor: Section 3.4: Memory access instructions on page 68 Section 3.5: General data processing instructions on page 80 Section 3.6: Multiply and divide instructions on page 108 Section 3.7: Saturating instructions on page 124 Section 3.8: Packing and unpacking instructions on page 132 Section 3.9: Bitfield instructions on page 136 Section 3.10: Floating-point instructions on page 148 Section 3.11: Miscellaneous instructions on page 170 3.1 Instruction set summary The processor implements a version of the thumb instruction set. Table 21 lists the supported instructions. In Table 21: • Angle brackets, <>, enclose alternative forms of the operand • Braces, {}, enclose optional operands • The operands column is not exhaustive • Op2 is a flexible second operand that can be either a register or a constant • Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions. Table 21. Cortex-M4 instructions Mnemonic Operands Brief description Flags Page ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V 3.5.1 on page 82 ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V 3.5.1 on page 82 ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V 3.5.1 on page 82 ADR Rd, label Load PC-relative address — 3.4.1 on page 69 |
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