PM0214 datasheet(79/245 Pages) STMICROELECTRONICS

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PM0214

The STM32 Cortex-M4 instruction set

244

Restrictions

In these instructions:

•

Do not use PC

•

Do not use SP for Rd and Rt

•

For STREX, Rd must be different from both Rt and Rn

•

The value of offset must be a multiple of four in the range 0-1020

Condition flags

These instructions do not change the flags.

Examples

MOV R1, #0x1

; initialize the ‘lock taken’ value try

LDREX R0, [LockAddr]

; load the lock value

CMP R0, #0

; is the lock free?

ITT EQ

; IT instruction for STREXEQ and CMPEQ

STREXEQ R0, R1, [LockAddr]

; try and claim the lock

CMPEQ R0, #0

; did this succeed?

BNE try

; no – try again

; yes – we have the lock

3.4.9

CLREX

Clear exclusive.

Syntax

CLREX{cond}

where:

‘cond’ is an optional condition code (see Conditional execution on page 64)

Operation

Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination

of the store exclusive if the exception occurs between a load exclusive instruction and the

matching store exclusive instruction in a synchronization operation.

See Synchronization primitives on page 33 for more information.

Condition flags

These instructions do not change the flags.

Examples

CLREX

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