PM0214 datasheet(30/245 Pages) STMICROELECTRONICS

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The Cortex-M4 processor

PM0214

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DocID022708 Rev 4

2.2.4

Software ordering of memory accesses

The order of instructions in the program flow does not always guarantee the order of the

corresponding memory transactions. This is because:

•

The processor can reorder some memory accesses to improve efficiency, providing this

does not affect the behavior of the instruction sequence.

•

The processor has multiple bus interfaces

•

Memory or devices in the memory map have different wait states

•

Some memory accesses are buffered or speculative.

Section 2.2.2: Memory system ordering of memory accesses on page 28 describes the

cases where the memory system guarantees the order of memory accesses. Otherwise, if

the order of memory accesses is critical, software must include memory barrier instructions

to force that ordering. The processor provides the following memory barrier instructions:

Use memory barrier instructions in, for example:

•

Vector table. If the program changes an entry in the vector table, and then enables the

corresponding exception, use a DMB instruction between the operations. This ensures

that if the exception is taken immediately after being enabled the processor uses the

new exception vector.

•

Self-modifying code. If a program contains self-modifying code, use an ISB

instruction immediately after the code modification in the program. This ensures

subsequent instruction execution uses the updated program.

•

Memory map switching. If the system contains a memory map switching mechanism,

use a DSB instruction after switching the memory map in the program. This ensures

subsequent instruction execution uses the updated memory map.

•

Dynamic exception priority change. When an exception priority has to change when

the exception is pending or active, use DSB instructions after the change. This ensures

the change takes effect on completion of the DSB instruction.

•

Using a semaphore in multi-master system. If the system contains more than one

bus master, for example, if another processor is present in the system, each processor

must use a DMB instruction after any semaphore instructions, to ensure other bus

masters see the memory transactions in the order in which they were executed.

Memory accesses to Strongly-ordered memory, such as the system control block, do not

require the use of DMB instructions.

For MPU programming, use a DSB followed by an ISB instruction or exception return to

ensure that the new MPU configuration is used by subsequent instructions.

DMB

The Data Memory Barrier (DMB) instruction ensures that outstanding memory

transactions complete before subsequent memory transactions. See DMB on

page 172.

DSB

The Data Synchronization Barrier (DSB) instruction ensures that outstanding

memory transactions complete before subsequent instructions execute. See DSB

on page 172.

ISB

The Instruction Synchronization Barrier (ISB) ensures that the effect of all

completed memory transactions is recognizable by subsequent instructions. See

ISB on page 173.

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