PM0214 datasheet(23/245 Pages) STMICROELECTRONICS

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PM0214

The Cortex-M4 processor

244

To access the exception mask registers use the MSR and MRS instructions, or the CPS

instruction to change the value of PRIMASK or FAULTMASK. See MRS on page 173, MSR

on page 174, and CPS on page 171 for more information.

Priority mask register

The PRIMASK register prevents activation of all exceptions with configurable priority. See

the register summary in Table 3 on page 17 for its attributes. Figure 5 shows the bit

assignments.

Figure 5. PRIMASK bit assignments

Fault mask register

The FAULTMASK register prevents activation of all exceptions except for Non-Maskable

Interrupt (NMI). See the register summary in Table 3 on page 17 for its attributes. Figure 6

shows the bit assignments.

Figure 6. FAULTMASK bit assignments

The processor clears the FAULTMASK bit to 0 on exit from any exception handler except

the NMI handler.

Table 8. PRIMASK register bit definitions

Bits

Description

Bits 31:1

Reserved

Bit 0

PRIMASK:

0: No effect

1: Prevents the activation of all exceptions with configurable priority.

Table 9. FAULTMASK register bit definitions

Bits

Function

Bits 31:1

Reserved

Bit 0

FAULTMASK:

0: No effect

1: Prevents the activation of all exceptions except for NMI.

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