PM0214 datasheet(14/245 Pages) STMICROELECTRONICS

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PM0214

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integration of the processor core and NVIC provides fast execution of interrupt service

routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the

hardware stacking of registers, and the ability to suspend load-multiple and store-multiple

operations. Interrupt handlers do not require any assembler stubs, removing any code

overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead

when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the STM32 to enter STOP or STDBY mode.

1.3.1

System level interface

The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide

high speed, low latency memory accesses. It supports unaligned data accesses and

implements atomic bit manipulation that enables faster peripheral controls, system

spinlocks and thread-safe Boolean data handling.

The Cortex-M4 processor has a memory protection unit (MPU) that provides fine grain

memory control, enabling applications to utilize multiple privilege levels, separating and

protecting code, data and stack on a task-by-task basis. Such requirements are critical in

many embedded applications such as automotive.

1.3.2

Integrated configurable debug

The Cortex-M4 processor implements a complete hardware debug solution. This provides

high system visibility of the processor and memory through either a traditional JTAG port or

a 2-pin Serial Wire Debug (SWD) port that is ideal for small package devices.

For system trace the processor integrates an Instrumentation Trace Macrocell (ITM)

alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling

of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of

software-generated messages, data trace, and profiling information through a single pin.

The optional Embedded Trace Macrocell™ (ETM) delivers unrivalled instruction trace

capture in an area far smaller than traditional trace units.

1.3.3

Cortex-M4 processor features and benefits summary

•

Tight integration of system peripherals reduces area and development costs

•

Thumb instruction set combines high code density with 32-bit performance

•

IEEE754-compliant single-precision FPU implemented in all STM32F4xxx and

STM32F3xxx Cortex-M4 microcontrollers

•

Power control optimization of system components

•

Integrated sleep modes for low power consumption

•

Fast code execution permits slower processor clock or increases sleep mode time

•

Hardware division and fast multiplier

•

Deterministic, high-performance interrupt handling for time-critical applications

•

Memory protection unit (MPU) for safety-critical applications

•

Extensive debug and trace capabilities: Serial Wire Debug and Serial Wire Trace

reduce the number of pins required for debugging and tracing.

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