GP2021 datasheet(8/62 Pages) MITEL

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GP2021

12 CHANNEL CORRELATOR

Fig. 4 shows a block diagram of the correlator. It consists

of the following blocks:

Clock Generator

The Clock Generator block divides the frequency of the

master clock CLK_T/CLK_I by 6 or 7 to give the internal multi–

phase set of clocks. When in Real_Input mode CLK_T/CLK_I

will normally be a 40MHz clock, which is divided by 7. When

in Complex_Input mode it will normally be at 35MHz which is

divided by 6. The SAMPCLK pin is an output giving a 4:3

mark–to–space ratio clock at 40 MHz / 7 (= 5·714MHz) in

Real_Input Mode.

The Clock Generator also produces the MICRO_CLK

signal at half the master clock frequency (20 MHz for

Real_Input mode, 17.5 MHz for Complex_Input mode) with a

1:1 mark–to–space ratio. This signal is output on the

MICRO_CLK pin in Standard Interface mode. However, its

main purpose is that of a synchronising clock to the memory

control logic in ARM System Mode and it is from this that the

processor clock output, MCLK, is derived.

Timebase Generator

The Timebase Generator produces 4 important timing

signals: ACCUM_INT, TIC, MEAS_INT and TIMEMARK.

ACCUM_INT is an interrupt provided to control data transfer

between the correlator accumulators and the microprocessor.

It may be detected by means of the ACCUM_INT output or by

reading the ACCUM_STATUS_A register (where bit 15 is a

flag indicating that ACCUM_INT has occurred since the

previous read of this register). ACCUM_INT is cleared by

reading ACCUM_STATUS_A.

After power–up this interrupt occurs every 505.05

µs. Its

period can subsequently be changed in one of 3 ways:

1) toggling the FRONT_END_MODE bit of the

SYSTEM_SETUP register,

2) toggling the INTERRUPT_PERIOD bit of the

SYSTEM_SETUP register, or

3) writing directly to the PROG_ACCUM_INT register.

See section ‘‘Detailed Description of Registers” on page 25 for

more information.

TIC is an internal signal with a default period of

99999.90

µs. It is used to latch measurement data (Epoch

count, Code phase, Code DCO phase, Carrier DCO phase

Fig. 4 Correlator block diagram

and Carrier cycle count) of all 12 channels at the same instant.

Its period can subsequently be changed, by writing to the

PROG_TIC_HIGH and PROG_TIC_LOW registers, or

toggling

the

FRONT_END_MODE

bit

the

SYSTEM_SETUP register.

MEAS_INT is a signal derived from the TIC counter. It may

be used by the microprocessor as a software module

switching interrupt either by using the MEAS_INT output or by

reading the ACCUM_STATUS_B or MEAS_STATUS_A

each TIC so long as the TIC period is greater than 50 ms. If the

TIC period is less than 50 ms, MEAS_INT is activated only at

each

TIC.

cleared

reading

either

the

ACCUM_STATUS_B or MEAS_STATUS_A register,

depending upon the MEAS_INT_SOURCE bit of the

SYSTEM_SETUP register.

TIMEMARK is also derived from TIC and may be output on

one of the discrete output pins. This signal is intended to be

used as an accurate 1 Pulse Per Second timing reference,

aligned to UTC (Universal Time Co–ordinated system), with a

pulse width of 1ms.

TIMEMARK has two methods of operation but in both

TRACKING

MODULE

CHANNEL 0

TRACKING

MODULE

CHANNEL 1

TRACKING

MODULE

CHANNEL 2

TRACKING

MODULE

CHANNEL 3

TRACKING

MODULE

CHANNEL 11

SELECTS

ADDRESS

DECODER

A<9:2>

32 BIT BUS

D<15:0>

CONTROL

BUS

INTERFACE

STATUS

REGISTERS

SYSTEM STATUS

MULTI–

PHASE

CLOCKS

CLOCK

GENERATOR

CLK_T

CLK_I

SAMPCLK

MICRO_CLK

MEAS_INT

ACCUM_INT

TIMEBASE

GENERATOR

TIC

INTERNAL

SAMPCLK

LATCHED

SIGN0 & MAG0

LATCHED

SIGN1 & MAG1

SAMPLE

LATCH

SIGN0 &

MAG0

SIGN1 &

MAG1

POWER SUPPLY

BITS

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