GP2021 datasheet(38/62 Pages) MITEL

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GP2021

PERIPHERAL FUNCTIONS REGISTERS

The addresses for the Peripheral Functions Registers

are shown in the GP2021 Register Map.

These registers may be either 8 or 16 bits wide. Registers

which are byte wide are accessed via the top 8 bits of the data

bus, D<15:8>. During a byte wide read D<7:0> are held Low.

Each of the registers for the Real Time Clock, Dual UART,

System and General Control functions are described below.

Real Time Clock and Watchdog

The registers in the Real Time Clock are all byte wide.

RTC_LS,

RTC_2ND,

RTC_MS ,

(Read Addresses)

The clock time is output in these three eight bit read only

registers. All three registers are latched when a read is

performed of the LS Byte Register, so this should be read first.

In Power Down Mode the clock continues to run but access to

these registers is not possible.

CLOCK RESET

(Write Address)

A write to this address resets the clock divider and

counter, regardless of the data word written.

WATCHDOG RESET

(Write Address)

A write to this address resets the watchdog timer,

regardless of the data word written.

DUART

All the registers within the DUART are byte wide.

CONFIG_A,

CONFIG_B

(Write Address)

These registers allow the UARTs to be configured for

receive baud rate, parity and loopback. The configuration bit

functions are shown in Table 15. The missing binary

combinations of bit settings should not be used as the results

would be indeterminate.

Note that all bits are set Low by a UART A/B or a System reset,

thus causing UART A/B to default to a receive baud rate of

300, no parity and no loopback.

STATUS_A,

STATUS_B

(Read Address)

Reading from these register addresses will give the

current value of the channels status bits. The Status bit

functions are as shown in Table 16.

Bit

SET (High) by

CLEARER (Low) by RESET to

RX Valid Data

No RX Data

Low

Available

RX FIFO Full

RX FIFO Not Full

Low

RX FIFO

Read of UART Status

Low

Overflow

TX Register Empty

Low

Transmitting

TX FIFO Full

TX FIFO Not Full

Low

Parity Error

Read of UART Status

Low

Occured

Low

Framing Error

Read of Uart Status

Low

Not Used

(Held High)

Table 16: Status bits available when reading the

STATUS_A and STATUS_B registers.

Table 15: Configuration of UARTs through CONFIG_A

and CONFIG_B registers.

Bit Setting

Function

Bit

Receiver Baud Rate

300

600

1200

2400

4800

9600

19.2k

38.4k

76.8k

Bit

Parity

No parity–bit not set or

checked for

Odd parity–parity added

so that the toatl number

of '1's in the word is even

Even parity–parity added

so that the total number

of '1's in the word is even

Bit

Loopback

No loopback–normal

operation

Loopback–the Tx output

drives the Rx input and

Tx pin is held HIGH

Bit

Test mode

Test mode bit in Ch A

only used for chip testing

only. This bit must be set

Low for Normal operation

Test mode

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