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GP2021 数据表(PDF) 14 Page - Mitel Networks Corporation |
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GP2021 数据表(HTML) 14 Page - Mitel Networks Corporation |
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14 / 62 page ![]() 14 GP2021 PLL_LOCK NRESET_OP MICRO_CLK 4 CYCLES MCLK 50ms NRESET_IP NRESET_OP MICRO_CLK 4 CYCLES Fig. 11 : PLL_LOCK Hardware Reset Generation Fig. 12 : NRESET_IP Hardware Reset Generation Discrete I/O The GP2021 contains a number of pins which may be used as discrete inputs or discrete outputs for general purpose system monitoring and control applications. The actual pins which may be used for each function vary according to the application and the interface mode of the GP2021.Table 5 shows a list of possible discrete inputs and outputs and the modes in which they may be used. The level on all discrete inputs can be read from the IO_CONFIG register. The status of the DISCIP pin may also be read from ACCUM_STATUS_B. The discrete outputs are controlled via either the SYSTEM_SETUP or IO_CONFIG registers. Discrete Inputs Pin Name Read Location Conditions for use as Discrete Input NRW/DISCIP3 IO_CONFIG Standard Interface mode. NOPC/NINTELMOT IO_CONFIG ARM System mode (debug disabled). NMREQ/DISCIP2 IO_CONFIG Standard Interface mode. NBW/WRPROG IO_CONFIG Motorola mode only. DISCIO IO_CONFIG DISCIO configured as discrete Input. NBRAM/DISCIP4 IO_CONFIG Standard Interface Mode. MULTI_FN_IO IO_CONFIG MULTI_FN_IO configured as discrete input. SIGN0, MAG0 IO_CONFIG Single real input mode (GP2010 or GP2015) front end using SIGN0, MAG0. SIGN1, MAG1 IO_CONFIG Single real input mode (GP2010 or GP2015) front end using SIGN1, MAG1. DISCIP1 IO_CONFIG Always available – dedicated Discrete Input. ACCUM_STATUS_B RXA IO_CONFIG UART Channel A not used. RXB IO_CONFIG UART Channel B not used. Discrete Outputs Pin Name Configuration Possible Outputs Location DISCOP SYSTEM_SET_UP High, Low, CH0 Dump, TIMEMARK, 100kHz Square Wave, Scan Out. DISCIO IO_CONFIG High, Low, TIMEMARK, 100kHz Square Wave. MULTI_FN_IO IO_CONFIG High, Low, TIMEMARK, 100kHz Square Wave. Table 5 : Discrete Input/Output Configuration |
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