GP2021 datasheet(40/62 Pages) MITEL

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GP2021

DATA_RETENT

(Write / Read Address)

This is a byte wide Read/Write register which can be used

to store a predetermined value, which can be interrogated in

order to determine whether a total power loss (below the data

retention level ) has occurred.

General Control

IO_CONFIG

(Write / Read Address)

The IO_CONFIG register is a full 16 bit wide read/write

location which allows the controlling microprocessor to view

the input level on all the Discrete and Multi Function inputs,

and a 16 bit wide write location for configuration of the

Discreteand Multi Function I/O pins.

IO_CONFIG Read: A read of the IO_CONFIG address

will latch the logic level of a number of input pins and output

these levels to the microprocessor via the 16 bit data bus. This

allows the microprocessor to read the input levels on all the

Discrete and Multi Function Inputs from a single location. The

bit allocations are as follows:

Bit

Input Pin

RXB

RXA

DISCOP

DISCIP

MAG1

SIGN1

MAG0

SIGN0

MULTI_FN_IO

NBRAM

DISCIO

NARMSYS

NBW/WRPROG

NMREQ

NOPC/NINTELMOT

NRW

It should be noted that the usefulness of a number of these

inputs as Discrete Inputs for System Control is dependant

upon the Interface Mode of the GP2021. For instance it is

possible to use the NOPC/NINTELMOT pin as a Discrete

Input in ARM System mode if the DEBUG function is disabled,

whereas this pin could not be used as a Discrete Input in

Standard Interface Mode. Similarly, NMREQ could be used

as a Discrete Input in Standard Interface Mode but not in ARM

System Mode.

IO_CONFIG Write: The IO_CONFIG write location

allows the configuration of the multi purpose I/O pins DISCIO

and MULTI_FN_IO. The register bit assignments are as

follows:

Bit

Bit Name

15 to 13

Not Used

MULTI_FN_IO_SELECT_TIMEMARK

MULTI_FN_IO_SELECT_100KHZ

MULTI_FN_IO_LEVEL

9 to 8

MULTI_FN_IO_CONFIG

7 to 4

Not Used

DISCIO_SELECT_TIMEMARK

DISCIO_SELECT_100KHZ

DISCIO_LEVEL

DISCIO_CONFIG

DISCIO_CONFIG: When set High this bit configures the

DISCIO pin as a Discrete Output, when low the DISCIO pin is

configured as a Discrete Input. A Master Reset sets the

DISCIO_CONFIG bit Low.

DISCIO_SELECT TIMEMARK,

DISCIO_SELECT_100KHZ,

DISCIO_LEVEL:

When configured as an output, the DISCIO pin can be

setup to give a signal as determined by Table 20.

At power on reset, the DISCIO output value = 0 setting is

chosen. The 100kHz square wave is derived from the Master

Clock and is useful for measuring its drift.

MULTI_FN_IO_SELECT TIMEMARK,

MULTI_FN_IO_SELECT_100KHz,

MULTI_FN_IO_LEVEL:

When configured as an output, the MULTI_FN_IO pin

can be setup to give a signal as shown in Table 21

Bit

DISCIO output value

100kHz square wave

TIMEMARK

Table 20: DISCIO output selection.

Bit

DISCIO output value

100kHz square wave

TIMEMARK

Table 21: MULTI_FN_IO output selection.

GP2021 数据表(PDF) 40 Page - Mitel Networks Corporation

GP2021 数据表(HTML) 40 Page - Mitel Networks Corporation

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