GP2021 datasheet(36/62 Pages) MITEL

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GP2021

FRONT_END_MODE: Selects either Real_Input mode

when Low or Complex_Input mode when High. Master reset

forces FRONT_END_MODE to Low.

INTERRUPT_ENABLE: When set Low the effect of the

ACCUM_INT and MEAS_INT interrupts are disabled

(masked) and when set High both are enabled. Master reset

forces INTERRUPT_ENABLE to Low.

Bits 4 to 1 The signal provided on the DISCOP pin can be

selected according to Table 14.

CARRIER_MIX_DISABLE: When High the Carrier

mixers are all driven by a fixed ‘+1’ level on the Carrier DCO

input port, so that the input data is passed unaltered to the

Code

mixer.

Master

reset

forces

the

CARRIER_MIX_DISABLE bit to Low.

TEST_CONTROL

(Write Address)

Bit

Bit Name

15 to 12 Not Used

11 to 9

PATH_SEL<2:0>

8 EN_SCANPATH

7 Not Used

6 TEST_CACODES

5 TEST_DATA

4 TEST_SOURCE

3 TM_TEST

2 FE_TEST

1 EN_DUMMYTICS

0 EN_DUMMYDUMP

This register is purely to enable various test modes. A

Master Reset will set all bits to Low, giving normal operation.

EN_DUMMYDUMP: When High, this bit changes the

function of the NOPC/NINTELMOT input pin to be a

DUMMYDUMP input, and if in Standard Interface Mode it also

forces the microprocessor mode to Motorola. A

DUMMYDUMP will operate in the same way as a normal

DUMP (reset all of the code generators and transfer the

contents of all integrators into the Accumulated Data

registers). Each Low to High transition of NOPC/NINTELMOT

will cause a DUMMYDUMP and if NOPC/NINTELMOT is

already High when EN_DUMMYDUMP is set, one will also

occur immediately. Selecting Dummy dump mode does not

inhibit normal DUMP events. The NOPC/NINTELMOT pin

must be held High for at least 200 ns for each DUMMYDUMP.

EN_DUMMYTICS: When High this bit changes the

function of the DISCIP input pin to a DUMMYTIC input. This

replaces the TIC from the timebase generator so that a TIC

effect will only occur when there is a Low to High transition on

DISCIP, to latch new Measurement Data. The DISCIP pin

must be held High for at least 200 ns for each DUMMYTIC.

FE_TEST: When High this test control forces the SIGN

input to channel 11 and the MAG input to channel 5 both to

Low. This allows the evaluation of the front_end SIGN (on

channel 5) and MAG (on channel 11) duty cycles. The Front

end to be tested is selected by the SOURCESEL bits in

CH5_SATCNTL and CH11_SATCNTL.

To get the SIGN and MAG count correctly into the

accumulators, both the carrier and code mixers must be made

transparent.

The carrier mixing may be disabled by either: (1) Setting

CARRIER_MIX_DISABLE (bit 0 in SYSTEM_SETUP) to High

to force a +1 on the Carrier DCO inputs to all channels or, (2)

If continued position finding is required from the other

channels during the test, by setting CH5_ and

CH11_CARRIER_DCO_INCR to all 0’s, to give a constant

level (zero frequency). This level should be set to a known

value by putting channels 5 and 11 briefly into the reset state

(by using RESET_CONTROL register bits 6 and 12) during

the time their Carrier DCO’s are programmed to zero

frequency. This reset forces the phase to all 0’s and hence the

drives to the Prompt In–phase mixer to a fixed +1 and not a

randomly selected –2, –1, +1, or +2 that would result from just

setting the frequency.

The C/A code mixing must be disabled by setting

CODE_OFF/ONB

(bits

both

CH5_

and

CH11_SATCNTL) to High. However, as the period of the

count is set by the DUMPs from the Code Generator, the DCO

clock to the Code Generator must be set to the required

frequency by programming the Code DCO even though the

code output is disabled. A typical value is the frequency for the

nominal code chipping rate, so that the SIGN and MAG counts

are over a millisecond.

The results of monitoring the Front–end of the receiver

may be used for fault diagnosis and also for tuning the

parameters in the software for optimum satellite tracking with

the particular Front–end or SIGN/MAG duty cycle.

To find the duty cycle of the SIGN signal, channel 5 is

used. The In–phase accumulator CH5_I_PROMPT will add

+1 for each SIGN sample at High and will add –1 for each

SIGN sample at Low, so if the duty cycle is correct at 50%, the

sum will always be close to zero and only differ by the

imbalance of sampling at the beginning and end of the

integration period.

The duty cycle may be calculated as follows:

N = Total No of samples in integration period.

N SIGN1 = Total No of samples for which SIGN was

High.

N SIGN0 = Total No of samples for which SIGN was

Low.

ACC5 = Total value in the CH5_I_PROMPT

accumulator, as read after a DUMP.

N = N SIGN1 + N SIGN0 ,

ACC5 = N SIGN1 – N SIGN0

SIGN duty cycle = R S = N SIGN1 / N = (N + ACC5) / 2N

(nominally 0.50)

Bit

Signal On

DISCOP output

0 (Reset condition)

Timemark

Ch0 DUMP

100kHz Square wave

Table 10: TRACK_SEL bit settings for Tracking arm

code selection.

GP2021 数据表(PDF) 36 Page - Mitel Networks Corporation

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