GP2021 datasheet(21/62 Pages) MITEL

21 / 62 page

GP2021

Control Signals

In Standard Interface Mode (NARMSYS held high), the

microprocessor interface of the GP2021 consists of two mode

control pins, (NINTELMOT and WRPROG), and the control

signals themselves, (ALE_IP, NCS, WREN and READ; the

exact function of which is dependent upon the interface style

selected).

Motorola Style Interface

(NINTELMOT = ’1’, WRPROG = ’X’)

The WRPROG mode control pin is not used in Motorola

Interface mode and should be tied High or Low. The ALE_IP

(Address Latch Enable input) pin is used to transparently latch

the address lines A<9:2> to the GP2021. If these address lines

are already latched externally, this pin may be tied High. Note

that the internal ALE signal is inhibited during a read or write

strobe so the address lines may be changed once the read or

write strobe has become active. The WREN pin acts as a

WRITE/READ ENABLE strobe (active High) with the READ

pin selecting either a READ strobe (READ = ’1’) or a WRITE

strobe (READ = ’0’). In a similar way to the addresses being

latched during a read or write strobe, the READ signal is also

latched during a data strobe and may be changed towards the

end of the cycle.

The NCS pin is an active low chip select used to gate out

the internal read and write strobes. In Standard Interface

Mode, the GP2021 can best be visualised in terms of 3 signals,

ALE_INT, WRSTROBE_INT and RDSTROBE_INT, the

internal ALE, write strobe and read strobe signals. In Motorola

Style Interface Mode these signals are derived as follows:

ALE_INT=ALE_IP. (WRSTROBE_INT + RDSTROBE _INT)

WRSTROBE_INT = NCS.WREN.READ

RDSTROBE_INT = NCS.WREN.READ

INTEL 80186 Style Interface

( NINTELMOT = ’0’, WRPROG = ’0’)

In the 80186 Style Interface mode the ALE_IP acts as an

Address Latch Enable input ( as in Motorola mode), used to

transparently latch the address lines A<9:2> to the GP2021.

Similar to Motorola mode, if the addresses are latched

externally this pin may be tied High. Whereas Motorola mode

used a single strobe input and a Read/Write level to denote

read and write strobes, both INTEL modes use a pair of strobe

inputs, one for reads, and one for writes. In this mode, READ

acts as the active low read strobe ( READ =RDSTROBE) and

WREN the active low write strobe ( WREN= WRSTROBE).

NCS is the active low chip select used to gate out internal data

strobes.

ALE_INT=ALE_IP

WRSTROBE_INT = NCS.WREN

RDSTROBE_INT = NCS.READ

INTEL 486 Style Interface

(NINTELMOT = ’0’, WRPROG=’1’)

The Intel 486 Style Interface is similar to the 80186 style

interface, with similar separate read and write strobes. Some

of the later Intel microprocessors (notably the i486) have a

very small delay between the rising edge of ALE and the falling

edge of the read or write strobes. Due to the pre-charged

nature of the data–out bus of the Correlator, the address

inputs must remain stable throughout the read strobe, and the

small delay from ALE to read strobe would produce insufficient

address setup times for correct operation. The 486 style

interface mode removes this problem by gating both the read

and write strobes such that they are inhibited until the falling

edge of ALE_IP. The ALE_IP pin must not be tied High in 486

Style Interface mode.

ALE_INT= ALE_IP

WRSTROBE_INT = NCS. WREN. ALE_IP

RDSTROBE_INT = NCS. READ. ALE_IP

Reset

The NRESET_IP pin allows the GP2021 to be provided

with an external system reset.

For further information refer to System Reset in Standard

Interface Mode.

As shown in the GP2021 Register Map, register

addresses differ from those in ARM System Mode. In

particular in Standard Interface Mode the GP2021 address

bus interface is via A<9:2>, with NCS acting as its chip select

input. The address pins A0, A1 in ARM System Mode now

become the NRESET_IP and ALE_IP inputs. Hence,

depending upon the system configuration employed, A<9:2>

of the GP2021 could be connected to the microprocessor

address pins A<7:0>.

Fig.21 Standard Interface Mode

NOTE: NRESET_OP, ACCUM_INT, and MEAS_INT are not shown

NARMSYS

GP2021

WRPROG

NINTELMOT

NCS

ALE_IP

WREN

READ

MICRO_CLK

D<15:0>

A<9:2>

MICROPROCESSOR

Decode

High Address Lines

VSS

Address

Logic

GP2021 数据表(PDF) 21 Page - Mitel Networks Corporation

GP2021 数据表(HTML) 21 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载