GP2021 datasheet(41/62 Pages) MITEL

41 / 62 page

GP2021

MULTI_FN_IO_CONFIG: These 2 bits configure the

function of the MULTI_FN_IO input as follows:

Bits <9:8>

MULTI_FN_IO Function

Digital System Test Enable Input

TRIGGER Input

Discrete Input (See Description) /

Scan Clocks Input

Discrete Output

Master Reset sets bits 9 and 8 to Low.

MULTI_FN_IO as Digital System Test Enable Input:

Allows testing of the Digital Section of the System Board. In

this mode, when MULTI_FN_IO is High, the RXA pin replaces

the Differential Master Clock Inputs and the RXB pin acts as

an RTC Reset input. The PLL_LOCK Filter is also disabled.

For more information see the Digital System Test Mode

description.

MULTI_FN_IO as TRIGGER Input: The DEBUG function

is enabled if in ARM System mode and the MULTI_FN_IO pin

acts as the TRIGGER input to the DEBUG block. For more

information see the DEBUG Block Description.

MULTI_FN_IO as Discrete Input / Scan Clocks: In this

mode the pin has 2 functions: As a discrete input and as the

Scan Clocks Input for chip scan path testing. It should be noted

that the MULTI_FN_IO pin should only be used as a discrete

input with caution. Since the Master Reset default is for

MULTI_FN_IO to act as the Digital System Test Enable input

it must be guaranteed that anything driving this pin as a

discrete input must have a Low output until the IO_CONFIG

TEST_CONFIG (Write Address)

The TEST_CONFIG register is a 3 bit wide write–only

the Correlator but contains chip test control bits for Peripheral

Functions. The register bit assignments are as follows:

Bit

Bit Name

RTC_TEST_COUNT

RTC_RESET_ENABLE

WDOG_RESET_DISABLE

RTC_TEST_COUNT : When set High this bit splits up the

24 bit counter of the RTC which counts seconds into a number

of 4 bit counters to allow easier chip testing. The 24 bit RTC

Counter is not Scan Path Testable. A Master Reset sets the

RTC_TEST_COUNT bit Low.

RTC_RESET_ENABLE: When set High this bit enables

the RXB pin to act as an RTC Reset input, which then resets

the RTC and Watchdog counters whenever RXB is taken high.

This function is intended for factory testing of the GP2021. A

Master Reset forces the RTC_RESET_ENABLE bit Low.

WDOG_RESET_DISABLE: When set High this bit inhibits

the production of System Resets from the Watchdog counter,

without disabling the Watchdog Counter itself. This function is

intended for Scan Path Testing of the Watchdog and RTC

Counters.

Master

Reset

forces

the

WDOG_RESET_DISABLE bit Low.

DATA_BUS_TEST

(Write / Read Address)

This is a 16 bit read/write register, whose function is to allow

a simple test of the 16 bit wide data bus to be performed, by

writing a 16 bit number and by checking that the same value

can be read back.

ABSOLUTE MAXIMUM RATINGS

These are not the operating conditions, but are the absolute limits which if exceeded, even momentarily, may cause

permanent damage.

To ensure sustained correct operation the device should be used within the limits given under Electrical Characteristics.

It is essential for bothV DD and V SS to be present before input signals are applied.

Supply Voltage (V DD ) from ground (V SS ):

–0.3 to+6.0V

Input Voltage (any input pin):

SS –0.3V to V DD + 0.3V

Output Voltage (any output pin):

SS –0.3V to V DD +0.3V

Storage Temperature:

–55

°C to +150°C

Electrostatic Discharge Protection (ESD)

The device is able to withstand an electrostatic discharge level of 2kV from 100pF through 1500 between any two pins in either polarity

(MIL. Std. 883 Human body model).

Crystal Specification

Frequency:

32.768kHz

Temperature range:

–40

ϒC to +85ϒC

Series resistance:

50k

Ω

Ω typ, 100Ω max

Load capacitance:

10pF typical

GP2021 数据表(PDF) 41 Page - Mitel Networks Corporation

GP2021 数据表(HTML) 41 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载