GP2021 datasheet(22/62 Pages) MITEL

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GP2021

CONTROLLING THE GP2021

The following section describes typical methods for

controlling the GP2021. These include: signal acquisition and

tracking, carrier phase measurement and timemark

generation.

Search Operation

To perform signal acquistion, the carrier frequency and

code phase space needs to be searched until the signal is

detected. The maximum carrier frequency excursion from its

nominal value is defined by the maximum carrier Doppler shift

plus the maximum receiver clock error. The maximum code

phase is defined by the (fixed) code length. Typically, all code

phases will be searched at a given carrier frequency before

advancing to the next carrier frequency bin and repeating the

code phase search.

Carrier DCO Programming

The following registers:

CHx_CARRIER_DCO_INCR_HIGH

(or X_DCO _INCR_HIGH),and

CHx_CARRIER_DCO_INCR_LOW are programmed in

sequence with the relevant data according to the frequency

bin being searched. It is always necessary to write to both the

_HIGH and _LOW registers. Carrier DCO programming will

become effective as soon as the channel is released (made

active). If the channel is already active, writes to

CHx_CARRIER_DCO_INCR_LOW

are

effective

immediately. (A small delay of up to 175ns will occur, to allow

synchronisation of the processor write operation to the chip

operation.)

Code DCO Programming

The CHx_CODE_DCO_INCR_HIGH

(or X_DCO_INCR_HIGH)

and the CHx_CODE_DCO_INCR_LOW registers are

programmed in sequence with the relevant data according to

the estimated code frequency offset. It is always necessary to

write to both _HIGH and _LOW registers. Code DCO

programming will become effective as soon as the channel is

released (made active). If the channel is already active, writes

to CHx_CODE_DCO_INCR_LOW are effective immediately.

(A small delay of up to 175ns will occur to allow

synchronisation of the processor write operation to the chip

operation).

Code Generator Programming

For each channel, the CHx_SATCNTL register is

programmed as follows:

(i)

Set the SOURCESEL bit to select the input signal source.

(ii)

Set the TRACK_SEL bits to set the Tracking arm code to

either early or late (with respect to the Prompt arm).

(iii) Set the G2_LOAD bits to select the required PRN code.

(iv) Program the CHx_CODE_SLEW register with the

desired code phase offset. The slew operation will

become effective upon CHx_RSTB release. The first

DUMP will generate accumulated data for the channel

and set the associated CHx_NEW_ACCUM_DATA

status bit.

(v) Release the relevant CHx_RSTB bits of the

RESET_CONTROL register to make the channel active.

When the code clock is inhibited (to slew the code phase)

the Integrate and Dump module is held reset. It will start to

accumulate correlation results only after the slew operation is

completed.

A search for a satellite on more than one channel may be

performed using the MULTI channel addresses and different

code slew values as appropriate.

Reading the Accumulated Data

each

DUMP

the

corresponding

CHx_NEW_ACCUM_DATA status bit is set in the

ACCUM_STATUS_A register. The status register, together

with

all

accumulation

registers

(CHx_I_TRACK,

CHx_Q_TRACK, CHx_I_PROMPT, CHx_Q_PROMPT) are

mapped into consecutive addresses. These can be read as a

consecutive block, if required, after every ACCUM_INT

interrupt. Alternatively, the Status Registers may be polled.

The Accumulation registers are not overwrite protected,

therefore the system must respond quickly when new data

becomes available. Whether or not it is necessary to process

the accumulation at every DUMP is dependent upon the

application. The order of reading them is optional, but ideally

the CHx_Q_PROMPT register should be read last, because

this resets the CHx_NEW_ACCUM_DATA bit.

The

CHx_MISSED_ACCUM

bits

the

ACCUM_STATUS_B register indicate that new accumulated

data has been missed. These can only be cleared by a write

to CHx_ACCUM_RESET or by deactivating the channel.

Search on Other Code Phases

When it is desired to correlate on the next code phase,

such as one whole chip later, the CODE_SLEW has to be

programmed with a value of 2 (the units are half code chips).

The slew will occur on the next DUMP. The effect of

CODE_SLEW is relative to the current code phase. To repeat

a CODE_SLEW, the register needs to be written to again even

if the same size slew is required.

Once the signal has been detected (correlation threshold

exceeded), the code and carrier tracking loops can be closed.

The tracking loop parameters must be tailored in the software

to suit the application.

Data Bit Synchronisation

The data bit synchronisation algorithm should find the

data bit transition instant. The processor calculates the

present one millisecond epoch and programs this value into

the 1MS_EPOCH counter. Ideally, epoch counter accesses

should occur following the reading of the accumulation

Alternatively, the epoch counters can be left free–running

and the offset can be added by the software each time it reads

the epoch registers. Note that if the integration is performed

across bit boundaries, the integration result can be very small.

Reading the Measurement Data

At each TIC, the measurement data is latched in the

Measurement Data registers

(CHx_EPOCH,

CHx_CODE_PHASE,

CHx_CARRIER_DCO_PHASE,

CHx_CARRIER_CYCLE_HIGH,

CHx_CARRIER_CYCLE_LOW,

CHx_CODE_DCO_PHASE ).

The ACCUM_STATUS_B or MEAS_STATUS_A

see if a TIC has occurred), otherwise measurement data will

be lost. The ACCUM_INT or MEAS_INT events can be used

GP2021 数据表(PDF) 22 Page - Mitel Networks Corporation

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