GP2021 datasheet(39/62 Pages) MITEL

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GP2021

Bit

Receiver Baud Rate

300

600

1200

2400

4800

9600

19.2k

38.4k

76.8k

TX_RATE_A,

TX_RATE_B

(Write Address)

These are write registers for UARTs A and B which allow

the Transmit baud rates to be set as shown in Table 17. The

missing binary combinations of bit settings should not be used

as the results would be indeterminate.

Note 1 . The conditions after a reset are:–

ROM wait states= 3, EEPROM and Spare wait states = 5+1.

SYSTEM_CONFIG

(Write / Read Address)

This is a Read/Write register (8 bits wide), which allows

the Watchdog Function to be enabled and disabled via bit 9.

Note that following a System reset this bit is set Low, thus

enabling the watchdog.

RESET_A,

RESET_B

(Write Address)

Writing to this register will reset the UART A/B, regardless

of the data word written.

TX_DATA_A,

TX_DATA_B,

RX_DATA_A,

RX_DATA_B

(Write / Read Address)

These are Read/Write addresses to UARTs A and B,

which allow bytes to be written to the TX FIFOs or received

from the RX FIFOs.

Table 17: Transmit baud rate settings in the TX_RATE_A

and TX_RATE_B registers.

Bits 12 to 15 are not used and may be set High or Low.

Note that bits 8 to 11 are set Low by a UART A/B or System

reset, thus causing the Transmitter to default to a baud rate of

300.

System Control

WAIT_STATE

(Write / Read Address)

This is a Read/Write register (8 bits wide), which allows

the ROM (Read/Write) wait state and EEPROM and Spare

(Read) wait states to be configured via bits 8 to 11. EEPROM

and SPARE read accesses consist of 2–5 wait states whilst

MCLK is High, increasing the read access time, followed by 1

trailing wait state whilst MCLK is Low to allow for a greater bus

release time. The Chip revision number appears on bits 12 to

15 when read.

Bit

ROM (Read/Write) Wait States

Unused (3)

Bit

EEPROM ans Spare (Read)

Wait States

2+1

3+1

4+1

5+11

Table 18: WAIT_STATE register settings.

Bits 15 to 10 and 8 are not used and could be set High or

Low. The Chip revision number appears on bits 12 to 15 when

read.

SYSTEM_ERROR_STATUS

This is an 8 bit wide Read only register, and allows the

source of a system reset to be determined via bits 11 to 8. It

is reset to all Low after being read. The Chip revision number

appears on bits 12 to 15 when read.

Bit 8

Set during a system reset , when the source of the

reset is a PLL_LOCK failure.

Bit 9

Set during a system reset, when the source of the

reset is the Watchdog.

Bit 10 :

Set during a system reset, when the source of the

reset is a POWER_GOOD failure.

Bit 11 :

Set during a system reset, when the source of the

reset is the external NRESET_IP. Note that

this reset source is only available in Standard

Interface Mode.

CHIP_REVISION

(Read Addresses)

The CHIP_REVISION register is a read only register

which exists as the high 4 data bits of the Wait State, System

Configuration and System Error Status registers. A read of

any of these three registers will output the CHIP_REVISION

information on bits 15 to 12. This register is intended to allow

software discrimination of revisions of the GP2021, both pre

production revisions and possible customer specific variants.

The initial production version of the GP2021 will have a

CHIP_REVISION of 0011.

Bit

Watchdog Function

Enabled

Disabled

Table 19: enableing the Watchdog function through the

SYSTEM_CONFIG register

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